Stmicroelectronics S.r.l.

Ovonyx Inc.

Sgs-thomson Microelectronics S.r.l.

Other

Western Digital (fremont), Inc.

Intel Corporation

Sgs Microelettronica Spa

Sgs-thomson Microelectronics S.p.a.

Giulio Casagrande

Roberto Gastaldi

Ferdinando Bedeschi

Fabio Pellizzer

Roberto Bez

Claudio Resta

Tyler A Lowrey

Ward D Parkinson

Paolo Giuseppe Cappelletti

Emilio Camerlenghi

Kyusik Sin

Matthew R Gibbons

Augusto Benvenuti

Hugh Craig Hiner

William D Jensen

Loris Vendrame

Rino Micheloni

Giovanni Campardo

Marco Pasotti

Richard Edward Fackenthal

Stephen J Hudgens

Raffaele Zambrano

Guy Charles Wicker

Wolodymyr Czubatyj

Xizeng Shi

Hua-Ching Tong

Ravi Annavajjhala

Edward J Spall

Xizeng (Stone) Shi

Paolo Cappeletti

A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.

Method for using a bit specific reference level to read a phase change memory

Using a bit specific reference level to read a memory

Using a bit specific reference level to read a resistive memory

A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.

Reading phase change memories

A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

Streaming mode programming in phase change memories

A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component having a terminal connected to a respective second conduction region.

Process for manufacturing an array of cells including selection bipolar junction transistors

A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Array of cells including a selection bipolar transistor and fabrication method thereof

An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof

In a method and system for reducing power consumed by a magnetic memory, magnetic memory cells are coupled to a bit line and are associated with a plurality of digit lines. A bit line current is provided in the bit line. Digit currents are provided in parallel in the digit lines at substantially the same time as the bit line current. The digit and bit line currents allow the magnetic memory cells to be written to a plurality of states in parallel.

Method and system for controlling MRAM write current to reduce power consumption

A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.

Writing circuit for a phase change memory device

A magnetic random access memory (MRAM) device has increased &#x394;R/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing &#x394;R/R. The plural transistors can share a source region.

Magnetic memory cell with plural read transistors

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Vignate, Italy

Giulio Casagrande