Micron Technology Incorporated

Intel Corporation

Stmicroelectronics S.r.l.

Micro Technology, Inc.

Giulio Albini

Paolo Tessariol

Roberto Somaschini

Alessandro Vaccaro

Emanuele Confalonieri

Paola Bacciaglia

Marcello Mariani

Umberto Maria Meotto

Alessandro Grossi

Fabio Pellizzer

Stephen W Russell

Max F Hineman

Anna Maria Conti

Sanjay Rangan

Carlo Cremonesi

Francesco Mastroianni

Giorgio Servalli

Emilio Camerlenghi

Methods, systems, and devices for low resistance via contacts in a memory device are described. A via may be formed so as to protrude from a surrounding material. A barrier material may be formed above an array area and also above the via. After a first layer of an access line material is formed above the barrier material, a planarization process may be applied until the top of the via is exposed. The planarization process may remove the access line material and the barrier material from above the via, but the access line material and the barrier material may remain above the array area. The first layer of the access line material may protect the unremoved barrier material during the planarization process. A second layer of the access line material may be formed above the first layer of the access line material and in direct contact with the via.

Low resistance via contacts in a memory device

Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Forming array contacts in semiconductor memories

Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.

Methods of forming integrated circuit devices

Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells.

Semiconductor device structures with improved planarization uniformity, and related methods

Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

Electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques

Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface

Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.

Memory device and method of fabricating thereof

Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Multi-interface memory with access control

Semiconductor structures and devices including conductive lines and peripheral conductive pads

Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.

Growing community of inventors

Boise, ID, United States of America

Giulio Albini