Texas Instruments Corporation

Giuliano Imondi

Sebastiano D'Arrigo

Sossio Vergara

Giulio Giuseppe Marotta

Giuseppe Savarese

Giulio Porrovecchio

Michael C Smayling

Sung-Wei Lin

Manzur Gill

Stefano Menichelli

Tito Gelsomini

Luciano Talamonti

Eros Pasero

Gill Manzur

Carlo Sansone

Field memories

Integrated circuit with a non-volatile variable resistor which is particularly adapted for use in a neuronic network. The integrated circuit comprises a symmetrically replicated structure including a floating gate MOS transistor (TRP; TRN) and an EEPROM memory cell based upon N-channel MOS transistors and including a read-out MOS transistor (TSP; TSN) and a tunnel-effect charge injection MOS element (TUNP; TUNN), with floating gates. The floating gates of all transistors and of the tunnel-effect element are connected together, with the ends of the resistor (R1P, R2P; R1N, R2N) being taken out from the source and drain regions of the floating gate MOS transistor.

Integrated circuit with non-volatile, variable resistor, for use in

Circuitry and a method are provided for selectively switching a negative voltage (-V.sub.nn) to portions of CMOS integrated circuits, which circuitry comprises a switching/decoding matrix. The switching/decoding matrix comprises a control and decode logic (CDL) which controls signal VPPENABLE to control a positive charge pump (PCP) producing positive voltage (+V.sub.pp) and which further controls signal VNNENABLE to control a negative charge pump (NCP) producing said negative voltage (-V.sub.nn). The switching/decoding matrix further comprises, for each line to be switched, a switching module which comprises a PMOS transistor (PS) having its source connected to said line and its drain connected to receive said negative voltage (-V.sub.nn) produced by said negative charge pump (NCP). The PMOS transistor (PS) gate is driven by a drive circuit being in turn driven by said control and decode logic (CDL) and connected so as to receive the positive voltage (+V.sub.pp) provided by said positive charge pump (PCP).

Circuitry and method for selectively switching negative voltages in CMOS

Data processing system implementing architecture of a neural network which is subject to a learning process, wherein the data processing system includes n.times.n synapses arranged in an array of j rows and i columns. A plurality of operational amplifiers respectively corresponding to the rows of the array are provided, with each operational amplifier defining a neuron. The input terminals of all of the synapses arranged in a respective column of the array are connected together and define n inputs of the neural network. The output terminals of the synapses arranged in a respective row of the array are connected together and serve as the inputs to a corresponding one of the plurality of operational amplifiers. Each synapse includes a capacitor connected between ground potential and the input terminal for weighting the synapse by storing a weighting voltage applied thereto. A random access memory has digitally stored voltage values for weighting all of the synapses. A plurality of digital-analog converters, one for each column of the array of synapses, are connected to the random access memory for converting the digital voltage values for weighting the synapses into analog voltage values. The digital-analog converters provide respective outputs to the weighting terminals of the synapses of a column via respective electronic switches for each synapse. Each row of the array includes a bistable circuit for driving the respective electronic switches under the control of a control section which also provides function commands and data to the random access memory.

Data processing system for implementing architecture of neural network

The subject of the invention is a learning system for a neural net physically insertable in the learning process, which comprises a detecting member for presenting to said neural net the basic information set that said neural net has to learn in order to provide a desired response; a microprocessor suitable to iteratively execute a learning algorithm based on a comparison among said basic information set itself, the response that the neural net provides and the response that one wants to obtain from the neural net (see FIG. 1).

Learning system for a neural net of a suitable architecture, physically

A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising a positive voltage switching circuit, a first isolating transistor, and a second isolating transistor. The positive voltage switching circuit may include an inverter with feedback transistor and a third isolating transistor. In one embodiment, the positive voltage switching circuit is capable of switching up to three positive voltage values and reference voltage to the wordline terminal.

Wordline driver circuit for EEPROM memory cell

A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising four P-channel transistors and two N-channel transistors as well as four switches. The circuit comprises a two-transistor inverter with a feedback transistor and three isolating transistors that prevent excessive currents and voltages from damaging internal and external circuit components.

Driving circuitry for EEPROM memory cell

A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of the memory element and providing output signal levels corresponding to the programmed states. A switch is coupled to the read circuit output and switches from an open to a closed position in response to a selected output signal level.

Electrically programmable fuse circuit for an integrated-circuit chip

A non-volatile memory device formed on a face of a semiconductor substrate which includes an array of electrically programmable read only memory cells, a Y address decoder coupled to said array and first and second sets of input/output lines coupled to said Y address decoder. Switch means isolates either the first or second set of input/output lines from the Y decoder. A programmable non-volatile memory element is coupled to programming ones of the input lines and is programmable into a programmed state from an unprogrammed state in response to a programming voltage applied to programming ones of the first set of input lines. A control circuit is coupled to the switch means and to the memory element for isolating the first or second set in response to an external signal applied to a selecting one of the first set of input/output lines and in response to the state of the non-volatile memory element.

Memory array with an array reorganizer

An array of electrically programmable semiconductor memory cells of a type having electrically conducting odd and even row lines, left and right column and ground lines and field oxide regions separating adjacent left and right cells. The array has a field plate over the field oxide region which extends underneath both odd and even row lines. A driver is coupled to the odd and even row lines in order to drive one of them to substantially ground potential while the other is driven high to a cell selection voltage.

Method of forming a field plate in a high voltage array

An integrated circuit oscillator which includes a capacitor, a reference current source coupled to the capacitor used to charge the latter, and a trigger circuit coupled to the capacitor having an upper input threshold for changing from a first state to a second state and a lower input threshold for changing from the second to the first state. A discharge circuit is coupled to the trigger circuit and is operative to discharge the capacitor in response to the trigger circuit changing states and to cease the discharging on changing back to its original state.

Method and circuit for trimming the frequency of an oscillator

A device for controlling the states of various parts of a main circuit during 'power-on' operations which includes an auxiliary circuit for generating a disabling signal when the value of the main circuit supply voltage is below a threshold value for use in disabling the parts of the main circuit.

Power-up control circuit including a comparator, Schmitt trigger, and

A circuit for sensing a voltage present on an input line higher than a supply voltage V.sub.DD which includes an isolation switch coupled between the input line and an output line, a threshold adjustment diode coupled in series with the isolation switch also between the input and output lines for establishing a voltage above V.sub.DD at which the isolation switch turns on and a constant current source coupled from an output of the sensing circuit and ground.

High voltage pulse detector with controllable current consumption

An oscillator for an integrated circuit which includes a Schmitt trigger having an upper threshold voltage V.sub.H and a lower threshold voltage V.sub.L, a capacitor coupled between an input to the trigger and ground, a current generator coupled to the trigger input for charging the capacitor at a constant rate and a current generator coupled to the trigger input for discharging the capacitor at a constant rate. A charge switch in series with the charging current generator reversibly couples the charging current generator between a source of high voltage and the trigger input in response to a change in state of the trigger from a first state to a second state. A discharge switch in series with the discharging current generator reversibly couples the latter across the capacitor in response to a change in state of the trigger from the second state to the first state.

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Rieti, Italy

Giuliano Imondi