Xilinx, Inc.

Gitu Jain

Sandor S Kalman

Vinay Verma

Sanjeev Kwatra

Taneem Ahmed

Christopher H Kingsley

Jason Helge Anderson

Soren T Soe

Satyaki Das

A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

Multi-threaded deterministic router

In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.

Parallel process optimized signal routing

A method is provided for routing a circuit design netlist. Nets of the netlist are grouped into a plurality of sub-netlists. For each sub-netlist, nets of the sub-netlist are routed as a function of congestion between nets of the sub-netlist. Congestion between nets of other sub-netlists in the plurality of sub-netlists is not taken into account. If two or more nets of the netlist are routed through the same routing resource, a global congestion history data set is updated to describe congestion between all nets in the netlist, and the two or more nets of the netlist are unrouted. The two or more nets are each rerouted as a function of the global congestion history data set and congestion between nets of the same sub-netlist as the net.

Parallel signal routing

A method and apparatus for implementing incremental design changes. In various embodiments, primary outputs of a new design are compared for logical equivalence to corresponding primary outputs of a prior implementation. If the logic is equivalent, the implementation of the primary outputs from the prior implementation is reused to implement the corresponding primary outputs of the new design.

Incremental logic synthesis system for revisions of logic circuit designs

A method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device (PLD). The PLD includes a plurality of function blocks (FBs), and each FB includes one or more output pins. The output signals are organized into logical output banks (LOBs), the output signals in each LOB having a common voltage level. Each of the FBs is associated with an LOB. For each FB, one or more unplaced signals are selected for placement in the FB as a function of a number of unplaced output signals in the LOB with which the FB is associated (&ldquo;current LOB&rdquo;), a number of output pins in FBs associated with LOBs other than the current LOB, and a number of output pins in all FBs that are associated with the current LOB and that have no assigned output signals.

Method and apparatus for placing output signals having different voltage levels on output pins of a programmable logic device

A method for controlling power consumption and output slew rate in a programmable logic device, which is programmable to emulate a user-defined logic function. After placing and routing the user-defined logic function such that a plurality of paths are assigned to associated resources of the programmable logic device, a group of the resources associated with at least one path of the logic function which is constrained by a user-defined timing specification is identified. These resources are sorted according to their respective power consumption. A first sub-group of the resources is then identified which, when operated in a low power mode, minimizes power consumption of the programmable logic device while satisfying the user-defined timing specifications of all paths. Also, a second sub-group of the resources is identified which, when operated in a slow slew mode, minimizes noise at the output terminals of the programmable logic device while satisfying the user-defined timing specifications of all paths ending at that output terminal. A target PLD is then programmed in accordance with the placement arrangement, and the resources of the first and second groups are set to low power mode and slow slew mode, respectively.

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Los Gatos, CA, United States of America

Gitu Jain