Altera Corporation

Girish Venkitachalam

Peter John McElheny

Fangyun Richter

Che Ta Hsu

Irfan Rahim

Peter Smeys

Shuxian Chen

Bradley Jensen

Hugh Sung-Ki O

Priya Selvaraj

Deepa Ratakonda

Hai Dang

Kuan Yeow Leong

Susan Falk

A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.

Strain-enhanced transistors with adjustable layouts

A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.

Integrated circuit and a method to optimize strain inducing composites

An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.

Metal-insulator-metal capacitors between metal interconnect layers

Strain enhanced transistors with adjustable layouts

In an example embodiment, an EDA application creates a physical PCell from a CAD database that relates the physical PCell to a collection of expected mask layers. The EDA application auto-places an identifying text label with the physical and converts the physical PCell and the text label to a format that represents the physical PCell and the text label as sequence of drawn layers. The EDA application generates an equation that performs transformational operations on the drawn layers to create a sequence of derived layers, where the sequence of derived layers defines a collection of logical mask layers. The EDA application executes the equation and compares a derived layer to the expected mask layers, if the derived layer interacts with the derived layer for the text label. If the compared derived layer varies from the expected mask layers, the EDA application reports a variance based on the text label.

Automated verification of transformational operations on a photomask representation

Integrated circuit bond pads are provided for forming wire bonds to integrated circuit package pins. Each pad uses a bond pad structure that provides room for under-pad circuitry. The under-pad circuitry can be connected to other circuitry on the integrated circuit, thereby providing efficient use of circuit real estate. The bond pad structures are formed in the dielectric stack portion of the integrated circuit using dummy bond pads and bond pad support structures. Bond pad support structures may be formed from metal in metal interconnect layers. Vias may be used to connect the bond pad support structures to each other and to the dummy bond pads. Bond pad support structures may be formed in a polysilicon layer at the bottom of the dielectric stack. A contact layer contains metal plugs that connect the polysilicon bond pad support structures to the lowermost metal-layer bond pad support structures.

Integrated circuit bond pad structures

Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol that is not associated with generating a functional IC feature. The first symbol has a predetermined size and a predetermined shape. A predetermined location on a mask is also associated with the first symbol. A mask diagram on the mask is generated at least partially at the first predetermined location. The size and shape of the mask diagram is then compared with at least a portion of the first predetermined size and the first predetermined shape of the first symbol.

Growing community of inventors

San Jose, CA, United States of America

Girish Venkitachalam