Sandisk Technologies Inc.

Toshiba Memory Corporation

Kioxia Corporation

Girish Desai

Senthil Thangaraj

William Guthrie

Barada Mishra

Steven E Wells

Daniel Edward Tuers

Amit Jain

Narasimhulu Dharani Kotte

Mark Carlson

Venkata Krishna Nadh Dhulipala

Shay Benisty

Abhijeet Manohar

Yoav Weinberg

Tal Sharifie

Gary Lin

Philip Rose

Saswati Das

Robert Jackson

Oded Karni

Narasimhulu DharaniKumar Kotte

Julien Magretts

In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the first region in the first operation mode.

SSD architecture supporting low latency operation

In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.

Enhanced trim command support for solid state drives

A method of managing a solid state drive (SSD), comprising: storing a first set of data in a first plurality of non-volatile memory dies, the first plurality of non-volatile memory dies communicatively arranged in one or more first communication channels; storing a second set of data in a second plurality of non-volatile memory dies, the second plurality of non-volatile memory dies communicatively arranged in one or more second communication channels; generating a first set of system data corresponding only to the first set of data; generating a second set of system data corresponding only to the second set of data; and managing the first set of system data corresponding to the first set of data independently of the second set of system data corresponding to the second set of data, wherein the one or more first communication channel and the one or more second communication channel are communicatively coupled to one or more channel controllers, the one or more channel controls are communicatively coupled to a memory controller, and the first plurality of non-volatile memory dies and the second plurality of non-volatile memory dies are part of an array of non-volatile memory dies.

Set aware system data and mapping tables

Methods and systems are provided that execute reduced host data commands. A reduced host data command may be a write command that includes or is received with an indication of host data instead of the host data. The reduced host data command may be executed with a Direct Memory Access (DMA) circuit independently of a processor that executes administrative commands. In the execution of the reduced host data command, host data may be generated, metadata may be generated, and the generated host data and/or metadata may be copied into backend memory with the DMA circuit independently of the processor.

Reduced host data command processing

Systems, methods and/or devices are used to enable enhancing data integrity to protect against returning old versions of data. In one aspect, the method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses in a logical address space of the host, (2) mapping the set of logical block addresses to a set of physical addresses corresponding to physical pages of the storage device, and (3) performing one or more operations for each logical block specified by the set of logical block addresses, including: (a) generating metadata for the logical block, the metadata including a version number for the logical block, (b) storing the metadata, including the version number, in a header of a physical page in which the logical block is stored, and (c) storing the version number in a version data structure.

Data integrity enhancement to protect against returning old versions of data

Systems, methods and/or devices are used to enhance data integrity to protect against returning old versions of data. In one aspect, a method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses, (2) mapping, using a mapping table, the set of logical block addresses to a set of physical addresses, where the mapping table includes a plurality of subsets, and (3) performing operations for each subset of the mapping table that includes at least one entry corresponding to a logical block specified by the set of logical block addresses, including: (a) generating metadata for the subset, the metadata including a version number for the subset, (b) calculating a Cyclic Redundancy Check (CRC) checksum for the subset, and (c) storing the version number for the subset and the CRC checksum for the subset in a version data structure.

A storage module and method for virtual abort are disclosed. In one embodiment, a virtual abort of a read command is provided. The read command triggers a read operation that comprises reading data from the storage module's memory, processing the data by at least one processing module as the data moves along a data path from the memory to the storage module's host interface module, and then providing the data to a host via the host interface module. When an abort command is received, the storage module allows the data that is read from the memory to be processed by the at least one processing module as the data moves along the data path to the host interface module but prevents the host interface module from providing the data to the host. In another embodiment, a virtual abort of a write command is provided.

Storage module and method for processing an abort command

A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

Datapath management in a memory controller

Methods, systems, and computer readable media for solid state drive caching across a host bus are disclosed. According to one aspect, a method for solid state caching across host bus includes, during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bust interface for accessing a second RAM memory located on a host and separate from the first RAM, using the first RAM as a cache for storing a first portion of metadata, and using the second RAM as a cache for storing a second portion of metadata, where the second RAM is accessed by the SSD via the host bus interface.

Methods, systems, and computer readable media for solid state drive caching across a host bus

Buffer memory reservation techniques for use with NAND flash memory include dynamically reserving regions of the buffer memory, responsive to a read/write request. Where the read/write request includes a plurality of data transfer requests, following completion of a data transfer request, the reserved buffer space may be recycled for use in a further data transfer request or for other purposes. During fulfillment of a read request, a buffer region is reserved from a larger buffer pool for a time period significantly smaller than the time required to execute a sense operation associated with the read request. The reserved buffer region may be reused for unrelated processes during execution of the sense operation.

Growing community of inventors

Cupertino, CA, United States of America

Girish Desai