Sgs-thomson Microelectronics Limited

Stmicroelectronics Gmbh

Girish A Dixit

Fusen E Chen

Robert O Miller

Fu-Tai Liou

Frank R Bryant

Che-Chia Wei

Yih-Shung Lin

Timothy E Turner

Chiara Zaccherini

Che C Wei

Alexander Kalnitsky

A method for fabricating interlevel contacts in semiconductor integrated circuits provides for formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Method for fabricating interlevel contacts of aluminum/refractory metal alloys

A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. The oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.

Method for making transistor spacer etch pinpoint structure

A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.

Method for forming a metal contact

Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature

A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric layer is patterned and etched to form a plurality of dielectric regions exposing portions of the first conductive layer. A second dielectric layer is then formed over the dielectric regions and the exposed portions of the first conductive layer. A plurality of contact openings through the second dielectric layer are formed to expose portions of the first conductive layer and portions of the dielectric regions. A second conductive layer is then formed over the second dielectric layer and in the contact openings.

Method of forming a field programmable device

A method is provided for forming a contact opening or via of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first metal region is formed over an underlying region. A first insulating layer is formed over the integrated circuit. A second insulating layer is then formed over the first insulating layer. A portion of the second insulating layer is etched to expose a portion of the first insulating layer wherein the exposed first insulating layer and the remaining second insulating layer form a substantially planar surface. A metal oxide layer is formed over the exposed first insulating layer and the remaining second insulating layer. A photoresist layer is formed and patterned over the metal oxide layer. The metal oxide layer is then selectively etched to form a via exposing a portion of the first insulating layer. The first insulating layer in the via is then selectively etched to expose a portion of the first metal region. The photoresist layer is removed and a second metal layer is then formed over the metal oxide layer and in the via contacting the first metal region.

Structure and method of forming vias

A method for forming sloped contact corners of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first oxide layer is formed over the integrated circuit. An insulating layer is formed over the oxide layer. The oxide and insulating layers are then patterned and etched to form a contact opening to expose a conductive region underlying a portion of the oxide layer. A second oxide layer is formed in the bottom of the contact opening. The insulating layer is then reflowed to form rounded contact corners after which the second oxide layer is removed.

Method to imporve metal step coverage by contact reflow

Method of forming vias

A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.

Method of forming submicron contacts

A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.

Planar contact with a void

Method of forming a planar contact with a void

Integrated circuit device structure with dielectric and metal stacked

A method is provided for forming a transistor spacer etch endpoint structure of an integrated circuit, and an integrated circuit formed according to the same. A gate is formed over a portion of a substrate. A dielectric layer is formed over the integrated circuit and an oxide layer is formed over the dielectric layer. the oxide layer is patterned and etched to form sidewall oxide spacers on each side of the gate and over a portion of the dielectric layer. The dielectric layer not covered by the sidewall oxide spacers is then removed.

Transistor spacer etch pinpoint structure

A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening. The second conductive layer is then removed. A third conductive layer is deposited over the second dielectric layer and in the opening.

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Dallas, TX, United States of America

Girish A Dixit