Intersil Americas Inc.

Globalfoundries Inc.

International Business Machines Corporation

Giri N K Rangan

John Farley Ewen

Roger Levinson

John M Caruso

Santhosh Madhavan

Steven Mark Clements

Timothy Joseph Schmerbeck

Umesh Kumar Shukla

Santosh Nene

Rajesh Cheeranthodi

Sarabjeet Singh

Arun R Umamaheswaran

Lokesh Kumath

Patrick I Rosno

Suhas Shivaram

Shridha Tyagi

A transmission driver impedance calibration circuit and method. A circuit is disclosed that includes: a controller for controlling a set of switches; a comparator having an output that is coupled to the controller; and a first comparator input coupled to: a first selectable node coupled between a first p-type adjustable resistor segment (PSEG) and an external resistor; and a second selectable node coupled between a pair of internal resistors; and a second comparator input coupled to: a third selectable node coupled between a second PSEG and a tcoil resistor, the tcoil resistor being further coupled in series to a n-type adjustable resistor segment (NSEG); and a fourth selectable node coupled between the tcoil resistor and the NSEG.

Transmission driver impedance calibration circuit

A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system.

Implementing broadband resonator for resonant clock distribution

Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.

Generating a parallel data signal by converting serial data of a serial data signal to parallel data

A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.

Sigma-delta converter system and method

Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.

Generating negative impedance compensation

A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first filter coefficient and the consecutive difference values in a memory. The consecutive filter coefficients are generated by retrieving the first filter coefficient, and adding a first difference value to the first filter coefficient to generate a consecutive second filter coefficient. The first difference value corresponds to a difference between the first filter coefficient and the second filter coefficient. A consecutive next difference value is then added to the second filter coefficient to generate a consecutive next filter coefficient. The consecutive next difference value corresponds to a difference between the second filter coefficient and the consecutive next filter coefficient.

Methods and systems for compression, storage, and generation of digital filter coefficients

Circuits, methods, and apparatus that provide highly accurate DCPs. One example provides a DCP that includes a resistor string having taps that may be selected by a corresponding number of switches under the control of a digital word. To compensate for parasitic switch resistances and for variations in the values of the resistor sting caused by processing tolerances, a voltage-controlled resistor (VCR) is placed in parallel with the resistor string and switches. A control voltage generated using a control loop adjusts the parallel VCR such that the resistance seen across the DCP is the desired value. The control loop compares a reference resistor to loop components that are scaled to the resistor string, switches, and VCR. The reference resistor may be an external resistor or an internal resistor. If the resistor is internal, it may be trimmed, for example with lasers or fuses.

Architecture for a highly accurate DCP

A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer.

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Bengaluru, India

Giri N K Rangan