Stmicroelectronics S.r.l.

Stmicroelectronics (Rousset) Sas

Giovanni Matranga

Antonino Conte

Rosario Roberto Grasso

Gianbattista Lo Giudice

Carmelo Ucciardello

Mario Micciche

Alberto Jose' Di Martino

Francesco La Rosa

Maria Giaquinta

Francesca Grande

Diego De Costantini

Luca Lo Coco

Gianbattista Logiudice

Alberto Jose′ Di Martino

Rosanna Maria La Rocca

Giuseppe Compagno

Alberto Jose' Dimartino

Mario Micchche'

De Costantini Diego

Carmine D'Alessandro

A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Methods and devices for erasing non-volatile memory

A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

Methods and devices for wear leveling

A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.

Method for reducing a memory operation time in a non-volatile memory device and corresponding non-volatile memory device

A method for managing a flash memory device including pages of memory cells is described. The memory device may be erasable at the page level, and the pages may include operative pages for storing operative values and service pages for storing information relating to the erasing of the operative pages. In response to a request to erase selected operative pages, the method may include determining a service page in use among the service pages according to service information stored in the service pages, verifying the presence a service page to be erased, and applying an erasing pulse to each service page to be erased. The method may also include writing an address of the operative pages into the service page in use, erasing the selected operative pages, and writing a completion indication of the erasing of the selected operative pages into the service page in use.

Managing of the erasing of operative pages of a flash memory device through service pages

A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction terminal coupled to the input terminal for receiving the input voltage, a second conduction terminal coupled to the output terminal, and a control terminal coupled to the output of a first operational amplifier. The first operational amplifier may have a non-inverting input terminal for receiving a first reference voltage, and an inverting input terminal coupled to a first terminal of a divider circuit for receiving a second reference voltage.

Voltage regulator

A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.

Dynamic biasing circuit for a protection stage using low voltage transistors

A charge pump latch circuit is provided that includes at least one first and at least one second charge pump stage interconnected by an intermediate circuit node, and a stabilization stage connected to the intermediate circuit node and to control terminals of transistors of the first and second charge pump stages. The stabilization stage includes at least one first pair and at least one second pair of first and second enable terminals receiving suitable and distinct phase signals that ensure the turn-off of the stabilization stage during overlapping periods of the phase signals. Also provided is a method for using a stabilization stage to drive transistors in first and second charge pump stages that are interconnected by an intermediate circuit node.

Electronic circuit for generating low voltage and high frequency phases in a charge pump

An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.

Biasing circuit for EEPROM memories with shared latches

A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.

Charge pump system and corresponding method for managing voltage generation

A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

Reading circuit for a memory cell

A CMOS temperature sensor includes a first circuit portion for generating a voltage signal whose value increases with the temperature to be sensed, and a second circuit portion for generating an electric voltage signal whose value decreases with the temperature to be sensed. A comparator is provided as an output stage for comparing the values of both voltage signals. The generator element of the second circuit portion is a vertical bipolar transistor connected in a diode configuration.

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Catania, Italy

Giovanni Matranga