Stmicroelectronics Gmbh

Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Giorgio Pedrazzini

Giulio Ricotti

Domenico Rossi

Paolo Cordini

Massimo Pozzoni

Enrico M Ravanelli

Paolo Menegoli

Ernesto Lasalandra

Giovanni Frattini

Paola Galbiati

Alberto Salina

Luca Fontanella

Michele Palmieri

Luca Bertolini

Hin Sing Fong

Carlo Vertemara

Krishnamoorthy Ravishanker

Sandro Cerato

Francesco Tampellini

Giuseppe Scrocchi

Marco Casis

Bendetto Vigna

Chee Keong Chow

A multi-chip system in which at least one of the chips includes a performance parameter encoded thereon. After system assembly, the performance parameter can be obtained by a companion chip and used to automatically or semi-automatically fine tune the companion chip to the specific parameters of the at least one chip.

Performance tuning using encoded performance parameter information

An electronic device includes a motion sensitive power switching integrated circuit, which, in turn, includes a power switch connected between an input and an output, and a MEMS inertial sensing switch movable from a first position to a second position based upon motion thereof. The motion sensitive power switching integrated circuit also includes a detector operating the power switch to supply power to the output from the input based upon the MEMS inertial sensing switch moving from the first position to the second position. The first and second positions may be, respectively, a normally open position and a closed position. The device may be unpowered until the MEMS inertial sensing switch moves from the open to the closed position. The detector may generate a power on reset (POR) signal based upon the MEMS inertial sensing switch moving from the open to the closed position.

Electronic device including motion sensitive power switching integrated circuit and related methods

A control circuit controls a motor assembly having a coil and a movable arm. The control circuit includes a drive circuit that is coupled to the coil and that generates a drive signal in response to a control signal and a speed signal. The control circuit also includes a sensor circuit that is coupled to the drive circuit and to the coil and that generates the speed signal at a level that corresponds to the speed of the arm. In a disk drive, such a circuit can be used to control the movement of a read-write-head assembly during parking and unparking of a read-write head. The circuit monitors the speed of the head and uses this speed information as feedback to maintain the speed of the head within a specified range. This prevents damage to the head and other disk-drive components, particularly in a disk drive that incorporates a head parking platform.

Circuit and method for controlling the parking and unparking of a read-write head

A continuous automatic calibration system and apparatus using a delta-sigma modulation technique. A first time duration is set. The first time duration is a length of time in terms of clock counts for a calibration procedure. Then, a second time duration occurring during the first time duration is measured. The second time duration is a length of time in terms of clock counts that a counter is operational. A multiplying factor is determined by dividing the first time duration by the second time duration.

Sigma-delta ramp loading calibration

An electronic device for driving an actuator device for a hard disk and a motor for turning the hard disk, the device having a first driving circuit connected to the rotation motor and integrated in a chip of semiconductor material having a substrate defining a reference-potential region, a second driving circuit integrated in the chip and connected to a first actuation stage of the actuator device, and a third driving circuit integrated in the chip and connected to a second actuation stage of the actuator device. The actuator device supports a read/write transducer of the hard disk. The first actuation stage performs a rough displacement of the read/write transducer, while the second actuation stage performs a finer displacement of the same read/write transducer.

Electronic device for driving an actuator device for a hard disk and for driving a motor that turns the hard disk

A multi-mode motor controller architecture includes a motor, an integrated circuit controller, and an integrated circuit driver circuit. The integrated circuit controller includes a pulse generator, a DAC, an ADC, and a digital compensator circuit. The integrated circuit driver circuit is in communication with the controller and includes an error amplifier, first and second output amplifiers for driving the motor, and a sense amplifier. The motor controller architecture is configurable to operate in a linear mode, a pulsed mode, or a switchable linear/pulsed mode. The controller architecture can be implemented with external compensation circuitry, such as a resistor-capacitor circuit, or with the digital compensation circuitry located within the controller integrated circuit.

Multi-mode motor controller chip set

A method and apparatus to control application of a drive current to a voice coil in a hard disk drive system modulates a periodic waveform between either a reference level and a signal associated with a stored back electromotive force (BEMF) in the voice coil. The drive current is applied to the voice coil during periods of time when the periodic waveform is modulated by the signal associated with the stored BEMF. The amplitude and duration of the drive current correspondingly decreases as the BEMF in the voice coil decreases. Thus, the voice coil is controlled based on its BEMF and is provided with decreasing power to move a head mechanism to or from a ramp assembly.

Method and apparatus for ramp loading in a hard disk drive using pulse width modulation

A voice coil motor control circuit provides control signals to a voice coil motor circuit drivel that is coupled to a voice coil motor. A current sensing resistor is coupled in series with the voice coil motor. The control circuit includes a sense amplifier having inputs that couple to the current sensing resistor and includes a feedback circuit that includes an input and also includes an output that couples to the voice coil motor driver. In a first mode of operation, the feedback circuit input is coupled to an output of the sense amplifier. The control circuit also includes an inverting operational amplifier. In the first mode of operation, the inverting operational amplifier is bypassed. In a second mode of operation corresponding to deployment of a read/write head from a parked position onto the disc, the inverting operational amplifier is coupled in series between the sense amplifier output and the feedback circuit input. As a result, a velocity of the voice coil motor is more precisely and accurately controlled.

Voice coil motor control circuit having alternative modes of operation and method of operation thereof

In a junction isolated integrated circuit including power DMOS transistors formed in respective well regions or in an isolated epitaxial region on a substrate of opposite type of conductivity, circuits are formed in a distinct isolated region sensitive to oversupply and/or belowground effects. These effects are caused by respective power DMOS transistors coupled to the supply rail or ground. These effects are alternatively controllable by specifically shaped layout arrangements, and may be effectively protected from both effects. This is achieved by interposing between the region of sensitive circuits and the region containing the power DMOS transistors for which the alternatively implementable circuital arrangements are not formed, the region containing the power DMOS transistors coupled to the supply rail or to a ground rail for which the alternatively implementable arrangements are formed. The special interposition separates and shields the sensitive circuits from the power device whose oversupply or belowground effect is not countered by specific circuit arrangements.

Belowground and oversupply protection of junction isolated integrated circuits

A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Method for suppressing parasitic effects in a junction-isolation integrated circuit

A driver circuit for controlling a piezoelectric actuator in a charge mode includes an amplifier having a first input terminal for receiving a control voltage, a second input terminal, and a main final stage with a main output terminal connected to the piezoelectric actuator. The amplifier also includes an additional final stage with an additional output terminal connected to the second input terminal. The main final stage and the additional final stage are connected in parallel with one another so that a current which passes through the main output terminal is proportional in accordance with a predefined factor to a current which passes through the additional output terminal. The driver circuit includes a device having a constant capacitance connected to the second input terminal so that an electrical charge transferred to the piezoelectric actuator is correlated with the control voltage in accordance with the predefined factor and the capacitance.

Driver circuit for controlling a piezoelectric actuator in charge mode

Method and device for suppressing parasitic effects in a

A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

Dual threshold current mode digital PWM controller

While employing the same number of dedicated pins of an IC, a self-configurable interface circuit between a control bus and the IC recognizes whether the IC is being used in a system employing an SPI or a I2CBUS protocol for the transmission to the IC of control signals through the bus. The interface circuit employs an 'inner' SPI interface standard block, to a third input of which either a true CE (chip-enable) signal coming from a third wire of the bus or a virtual CE signal that is self-generated by the interface circuit in case of operation in an I2CBUS environment, is fed. The third (ADDR) pin of the IC may be connected to the CE wire of the bus in case of an SPI application or it may be biased at the supply or ground voltage for selecting one or the other of two internal addresses of the IC, when functioning in an I2CBUS environment.

Integrated circuit interface to control bus with either of two different

The present invention relates to an integrated input/output interface for low and/or high voltage range signals of the digital and/or analog type. It comprises essentially a power amplification circuit block (2) having at least one low voltage range input terminal (A) and at least one high voltage range output terminal (B), and a second amplification circuit block (3) having a high voltage range input terminal connected to said high voltage range output terminal (B) and at least one low voltage range output terminal (D). A conventional circuit block (4) prevents a high voltage range signal being input to said high voltage range terminal (B) from propagating through the first power amplification circuit block (2), so that it only affects the second amplification circuit block (3). This interface is implemented in mixed high voltage bipolar/CMOS/DMOS technology.

Growing community of inventors

Rancho Santa Margarita, CA, United States of America

Giorgio Pedrazzini