Stmicroelectronics S.r.l.

Atmel Corporation

Dora S.p.a.

Giorgio Oddone

Paolo Rolandi

Lorenzo Bedarida

Massimo Montanaro

Simone Bartoli

Fabio Tassan Caser

Davide Manfre′

Riccardo Riva Reggiori

Stefano Sivero

Marco Giovanni Fontana

Andrea Sacco

Massimiliano Frulio

Paolo Caprara

Antonio Barcella

Mauro Pagliato

Mauro Chinosi

Loris Vendrame

Giorgio Bosisio

Domenico Attianese

Luca Figini

Andrea Bettini

Alberto Riva

A converter configured to convert a DC input voltage to a DC output voltage, may include: a high-side driver circuit having a first terminal coupled to a first die pad; a high-side transistor having a drain terminal coupled to a second die pad and a source terminal coupled to a third die pad; and a low-side transistor having a source terminal coupled to a fourth die pad and a drain terminal coupled to a fifth die pad. The converter may further include a resistive element coupled between the source terminal of the high-side transistor and the drain terminal of the low-side transistor, where a second terminal of the high-side driver circuit is coupled to a sixth die pad.

Converter configured to convert a DC input voltage to a DC output voltage and including at least one resistive element

Powering the internal circuitry, that is the controller of the power switch of a step-down DC-DC converter for a broad range of values of output voltage and achieving an enhanced energy saving in a low load conditions of operation is made possible by a method and implementing circuit based on defining two distinct thresholds of discrimination of the output voltage, both tied to a reference voltage, for generating two respective control signals and defining, from logical combinations of said two control signals, three distinct regions of operation of the converter upon the varying of electrical parameters, respectively identified by logical combinations of a pair of enabling signals.

Method for enhancing conversion efficiency at low load of a step-down DC-DC switching converter and related circuit

A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.

Flexible OTP sector protection architecture for flash memories

A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.

Method and system for reducing soft-writing in a multi-level flash memory

A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.

Method and apparatus for discharging a memory cell in a memory device after an erase operation

A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.

System and method for matching resistance in a non-volatile memory

A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.

Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device

A fast power-on band-gap reference circuit includes a buffer, a first band-gap logic, and a second high drive band-gap logic. During power-on of the band-gap reference circuit, both the first band-gap logic and the second high drive band-gap logic are activated, in which the first band-gap logic charges an output of the first band-gap logic and the second high drive band-gap logic charges a capacitance associated with an output of the band-gap reference circuit. When the output of the first band-gap logic reaches a predetermined value, the second high drive band-gap logic is deactivated and the output of the first band-gap logic is couple to the output of the band-gap reference circuit through the buffer.

Method and apparatus for fast power-on of the band-gap reference

An n-channel MOS transistor negative-voltage charge pump is disclosed in which the bulks of the n-channel MOS transistors are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.

Negative charge pump with bulk biasing

A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.

Temperature-compensated current reference circuit

A transistor includes a substrate region ( ) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region ( ) of the first type (P&plus;) of conductivity inside the substrate region ( ) and adjacent to a first terminal (C) of the transistor, a well ( ) of second type (N) of conductivity placed inside the substrate region ( ), wherein the well ( ) of second type (N) of conductivity includes at least a second contact region ( ) of a second type of conductivity (N&plus;) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions ( ) of the first type of conductivity (P&plus;) adjacent to a plurality of regions of a third terminal (E , . . . , E ) of the transistor interposed each one ( ) and other ( ) by proper insulating shapes ( ).

Multi-emitter bipolar transistor for bandgap reference circuits

The voltage applied to the gate terminals of the charging transistors and charge-transfer transistors of two parallel pumping branches forming a charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.

High-efficiency power charge pump supplying high DC output currents

A charge pump having a phase-generator circuit generating phase signals and an oscillator circuit supplying a clock signal, a current-limitation circuit to limit the current flowing in the oscillator circuit, and a control circuit supplying on an output a control signal supplied to the current-limitation circuit. The control circuit has a first current mirror connected to a ground line, a second current mirror connected to a supply line, a cascode structure arranged between the first and the second current mirrors and connected to the output of the control circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line, and a compensation circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line and by slow variations in temperature.

Low-consumption charge pump for a nonvolatile memory

A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

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Rossiglione, Italy

Giorgio Oddone