Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Sgs Microelettronica Spa

Ovonyx Inc.

Giorgio De Santi

Giuseppe Paolo Crisenza

Luca Zanotti

Giulio Iannuzzi

Livio Baldi

Gianfranco Cerofolini

Claudio Contiero

Giuseppe Corda

Aldo Losavio

Danilo Re

Maria Santina Marangon

Romina Zonca

Fabrizio Andreani

A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi, Ta, WSi, and the increase in resistivity is obtained by nitridation.

Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof

A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.

Process of final passivation of an integrated circuit device

A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.

Method for final passivation of integrated circuit

An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

Low dielectric constant composite film for integrated circuits of an

A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.

Process and structure for measuring the planarity degree of a dielectric

Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.

Process for forming semiconductor device having multi-thickness

The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

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Milan, Italy

Giorgio De Santi