International Business Machines Corporation

Giora Biran

Vadim Makhervaks

Leah Shalev

Renato John Recio

Richard Louis Arndt

Jaya Srikrishnan

Harvey Gene Kiel

Zorik Machulsky

Jan Van Lunteren

Christoph Hermann Hagleitner

Timothy Hume Heil

Amit Golander

Patrick Allen Buckland

Ilya Granovsky

Tal Sostheim

Hubertus Franke

Russell Dean Hoover

Julian Satran

Ilan Shimony

Hao Yu

Alper Buyuktosunoglu

Pradip Bose

Eric Oliver Mejdrich

Bernard Charles Drerup

Clarence Rosser Ogilvie

Phillip John Restle

Jamie Randall Kuesel

Tobias Webel

Robert Allen Drehmel

Richard Nicholas

Preetham M Lobo

Charles S Woodruff

Christos Vezyrtzis

Ramon Bertran Monfort

Erez Barak

Pierce I-Jen Chuang

Osher Yifrach

Amir Turi

Alexander Mesh

Ming-i Mark Lin

Mark E Kautzman

Luis E De La Torre

Claudiu Schiller

Jyoti Gupta

Timothy John Slegel

Christian Jacobi

Fadi Y Busaba

Lisa Cranton Heller

Mark S Farrell

Brian Mitchell Bass

Robert Spencer Horton

Shaul Yohai Yifrach

Igor Chirashnya

Ophir Erez

Lior Glass

Elchanan Perlin

Hrvoje Bilic

Georgy Machulsky

Adam James Muff

David Arnold Luick

Nobuyoshi Tanaka

Mark Owen Maxson

Nancy Anne Greco

James Anthony Marcella

Heather D Achilles

John Lewis Hufferd

Etai Adar

Eli Arbel

Kalman Zvi Meth

Uzi Shvadron

Avraham Ayzenfeld

Shai Ishaya Tahar

Kiyoshi Nishino

Mark Epshtein

Amit Shay

Leah Shaley

Ilya Gransovky

Matthew Adam Cushing

Allen James Gavin

Tai Sostheim

Vadim Makher-Vaks

A credit-based flow control system can utilize speculative credit. If an agent has not received a credit return from a downstream agent for a given period of time, the agent can return speculative credit to an upstream agent. This way, even if the agent is not currently capable of performing operations represented by the speculative credit, the upstream agent can be enabled to proceed with operations.

Data transmission flow control regime

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Proactive voltage droop reduction and/or mitigation in a processor core

Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Instructions controlling access to shared registers of a multi-threaded processor

An unobservable cycle for at least one latch in a circuit design is detected. The unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design. A coverage event is generated to identify the unobservable cycle for the at least one latch. The coverage event is tracked to detect a state associated with the unobservable cycle and a state change cycle. The state change cycle is determined based on a simulation technique. A redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle is determined. Furthermore, manufacturing of a circuit based on the circuit design is at least initiated. The circuit design is modified to prevent the redundant switching of the at least one latch.

Modifying circuits to prevent redundant switching

The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

Reducing clock power consumption of a computer processor

Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.

An apparatus and method of submitting hardware accelerator engine commands over an interconnect link such as a PCI Express (PCIe) link. In one embodiment, the mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting a remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs a co-processor request completion sequence (status update, write to flag, interrupt) included in the co-processor command.

Methods for the submission of accelerator commands and corresponding command structures to remote hardware accelerator engines over an interconnect link

Methods for the transmission of accelerator commands and corresponding command structure to remote hardware accelerator engines over an interconnect link

An apparatus and method of emulating a hardware accelerator engine over an interconnect link such as PCI Express (PCIe) link. In one embodiment, the accelerator emulation mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The accelerator emulation mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command.

Accelerator engine emulation over an interconnect link

A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Pattern matching engine for use in a pattern matching accelerator

Software and hardware managed dual rule bank cache for use in a pattern matching accelerator

Growing community of inventors

Zichron-Yaakov, Israel

Giora Biran