Intel Corporation

Ginger Gilsdorf

Francesc Guim Bernat

Karthik Kumar

Thomas Willhalm

Mark A Schmisseur

An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

Apparatuses, systems, and methods for invalidating expired memory

Examples relate to a method for a memory module, a method for a memory controller, a method for a processor, to a memory module controller device or apparatus, to a memory controller device or apparatus, to a processor device or apparatus, a memory module, a memory controller, a processor, a computer system and a computer program. The method for the memory module comprises obtaining one or more memory write instructions of a group memory write instruction. The group memory write instruction comprises a plurality of memory write instructions to be executed atomically. The one or more memory write instructions relate to one or more memory addresses associated with memory of the memory module. The method comprises executing the one or more memory write instructions using previously unallocated memory of the memory module. The method comprises obtaining a commit instruction for the group memory write instruction. The method comprises updating the one or more memory addresses based on the previously unallocated memory used for executing the one or more memory write instructions after obtaining the commit instruction for the group memory write instruction.

Concept for group memory write instructions

Technologies for dynamically allocating tiers of disaggregated memory resources include a compute device. The compute device is to obtain target performance data, determine, as a function of target performance data, memory tier allocation data indicative of an allocation of disaggregated memory sleds to tiers of performance, in which one memory sled of one tier is to act as a cache for another memory sled of a subsequent tier, send the memory tier allocation data and the target performance data to the corresponding memory sleds through a network, receive performance notification data from one of the memory sleds in the tiers, and determine, in response to receipt of the performance notification data, an adjustment to the memory tier allocation data.

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Chandler, AZ, United States of America

Ginger Gilsdorf