Industrial Technology Research Institute

Other

Computer & Communication Research Laboratories

Gin-Kou Ma

Muh-Rong Yang

Chiung-Shien Wu

Wen-Chung Liu

Shen-Iuan Liu

Li-Ren Huang

Tzu-Yi Yang

Che-Fu Liang

Chein-Wei Jen

Chi-Hung Lin

Tay-Jyi Lin

Pi-Cheng Hsiao

John-See Lee

A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

Performance scaling device, processor having the same, and performance scaling method thereof

A transmission method executed in a multiple input multiple output wireless communication system may include the following steps: receiving a transmitting bit sequence; providing an X level pulse amplitude modulation (X-PAM) signal set, wherein distances between any two adjacent signal points in the X-PAM are the same; generating M signal sets according to the X-PAM signal set, wherein the isignal set is formed by multiplying the X-PAM signal set with a parameter (1/X), wherein i is an integer from 1 to M, and generating a X-PAM signal set joint coding/decoding table according a superposition result of the M signal sets; generating M transmitting bit sub-sequences according to the transmitting bit sequence; generating M transmitting signals according to the M transmitting bit sub-sequences and the X-PAM signal set joint coding/decoding table; transmitting the M transmitting signals to a wireless transmission channel via M transmitting antennae.

Transmission method and multiple input multiple output wireless communication system using the same

A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.

Frequency synthesizer and frequency synthesizing method

A two-piece wireless hearing improvement system having a pocket piece and an earpiece, wherein the pocket piece includes a microphone adapted to receive analog signals, a first processor coupled to the microphone to convert the analog signals to digital signals, and a first transceiver coupled to the processor to transmit the digital signals. The earpiece includes a second transceiver for receiving the digital signals, a second processor coupled to the second transceiver for converting the digital signals to analog signals, a speaker coupled to the second processor for transmitting the analog signals, and a movement detector for detecting relative movements between the earpiece and the pocket piece and generating a first signal according to the relative movements. The first processor provides signal compensation based on the first signal.

Wireless system and method thereof for hearing

An ultra-wideband (UWB) transceiver for use in UWB communication includes a voltage-controlled oscillator (VCO) configured to periodically and sequentially generate a series of base frequencies based on a predetermined sequence and a waveform generator to generate carrier waves based on the generated base frequencies.

System and method for ultra-wideband (UWB) communication transceiver

A communications system that comprises a channel encoder for encoding a plurality of information bits, a mapping unit coupled to the channel encoder for mapping the plurality of information bits into a first set of quadrature phase shift keying (QPSK) symbols and a second set of QPSK symbols, wherein every successive predetermined number of information bits are mapped to a first QPSK symbol and a second QPSK symbol in one symbol period in accordance with a mapping table, a first modulation unit coupled to the mapping unit for converting the first QPSK symbol into a first QPSK constellation symbol, and a second modulation coupled to the mapping unit for converting the second QPSK symbol into a second QPSK constellation symbol.

Enhanced wireless communication system and method thereof

A transport protocol that meets the requirements and performance for multimedia data transfer in a wireless link includes a transmitting/sending station and a receiving station. The inventive protocol is referred to as the Burst-oriented Transport with Time-bounded Retransmission (BTTR). This scheme uses a large transmission window for sending/receiving a burst of time-sensitive data and, within this window, several smaller observation windows are used for dynamic error retransmission. There is a time limitation on each retransmission such that the burst of data can be received in a timely manner, and thus trading some packet losses (still in an acceptable range) for delay and throughput performance. Specifically, the wireless network includes a wireless station for transmitting data over a wireless link. The sending station transmits a plurality of sequential data packets to the receiving station, wherein each plurality of sequential data packets form a respective Group-of-Packet (GOP). The receiving station detects whether any of the received data packets in each current GOP are corrupted before receipt of all data packets in the current GOP. The receiving station then transmits a negative acknowledgement (ACK) packet to the sending station before the receipt of all data packets in the current GOP, if at least one data packet in the current GOP is corrupted. Note that the ACK packet indicates which data packets are corrupted. In addition, the sending station selectively retransmits the data packets based on the indication of the received ACK packet before transmitting the next GOP to the receiving station.

Data transfer method for wire real-time communications

A scalable server architecture for use in implementing scaled media servers capable of simultaneous real-time data stream retrieval for large numbers of subscribers. A scalable server includes a plurality of stream pumping engines each accessing a particular storage device of a storage subsystem, and a server processor which receives retrieval requests from subscribers and directs the stream pumping engines to retrieve the requested data streams. Each of the stream pumping engines may include a storage controller coupled to its corresponding storage device for directing retrieval of the requested stream therefrom, a network controller for supplying the retrieved stream to a client network, and a processor for directing the operation of the storage and network controllers. Each of the stream pumping engines may also include a shared memory accessible by the corresponding stream pumping engine processor and the server processor. The shared memory facilitates communication with other stream pumping engines via the server processor and server system bus. A scaled media server may be implemented by cross-connecting several scalable servers with a plurality of stream multiplexers. Each of the stream multiplexers can include a separate packet input unit for processing the packets of each media stream such that two distinct levels of transmission priority are provided and quality of server restrictions are satisfied for all streams.

Scalable architecture for media-on demand servers

A cable network is provided with at least one bridge that is connected to a first cable segment of the cable network. The bridge receives from a shared communication medium a first carrier signal, having a first carrier frequency that is allocated for intra cable segment packet communication, containing packets modulated thereon. The bridge demodulates selected packets originating in the first cable segment from the first carrier signal. The bridge modulates each of the demodulated packets, that are destined outside of the first cable segment, onto a second carrier signal having a second carrier frequency. The bridge then transmits the second carrier signal on an upstream link of the common shared medium.

Growable architecture for high-speed two-way data services over CATV

A system and method are provided for routing received cells through a switch fabric. A plurality of output channels are organized into a plurality of channel groups, wherein each of the channels groups is associated with one or more unique output ports of a Benes network. A plurality of cells destined to one or more of the plurality of channel groups is received at plural input queues. A different output port of the Benes network is selected for one or more of the input queues that contains a cell. Then, one cell is switched from each of one or more input queues through the Benes network to the respective selected output port.

Multiple channel ATM switch

Scalable architecture for media-on-demand servers

A system and method are provided for assigning routing tag bits for routing signals through a Benes network comprising an input stage and an output stage. The input and output stages each comprise a column of 2.times.2 .beta. elements which route an inputted signal to an upper output if the control sequence bit is 0 and to a lower output if the control sequence bit is 1. Each signal inputted to the Benes network is associated with control sequence. For a particular Benes, in a particular control stage of the Benes network, a 0 is assigned to a control sequence bit associated with a signal q.sub.0 received at an upper input of a topmost input stage .beta. element. A 1 is assigned to a control sequence bit associated with a signal q.sub.k received at the same output stage p element as the signal q.sub.0. A 1 is assigned to a control sequence bit associated with a signal q.sub.1 received at a lower input of the topmost input stage .beta. element. A 0 to is assigned to a control sequence bit associated with a signal q.sub.k ' received at the same output stage .beta. element as the signal q.sub.1. For at least one signal q.sub.p for which no control sequence bit is yet assigned, either a 0 or a 1 is assigned to the control sequence bit associated with the signal q.sub.p. The complement of the chosen control sequence bit is assigned to a control sequence bit associated with a signal q.sub.k ' received at the same output stage .beta. element as the signal q.sub.p.

Enhanced partially self-routing algorithm for controller Benes networks

A method and apparatus for storage and retrieval of multiple data streams in a multimedia distribution system. A given data stream is separated into a plurality of portions, and the portions are stored in a multi-disk storage system with Y disks each having X zones such that the ith portion of the given stream is stored in zone (i mod X) of disk (i mod Y). The number X of zones per disk and the number Y of disks are selected as relatively prime numbers. The stored data are retrieved using Y independent retrieval schedulers which are circulated among the Y disks over a number of scheduling intervals. Each retrieval scheduler processes multiple requests separated into X groups, with the requests of each group accessing the same disk zone during a given scheduling interval. The retrieval schedulers are also configured such that the retrieval requests of a given retrieval scheduler access the same disk during a given scheduling interval. The data stream placement technique in conjunction with the retrieval schedulers provide sequential-like parallel retrieval suitable for supporting real-time multimedia data distribution for large numbers of clients.

Media server for storage and retrieval of voluminous multimedia data

An inventive switch for transporting information cells without cell contention is described. The switch includes at least one parallel distribution network. Each distribution network includes an N.times.N first routing network for receiving cells at a plurality of input ports, where N equals the number the input ports. Illustratively, the routing network is self-routing and non-blocking, such as a Banyan Network. Connected to the N.times.N network are .rho..sup.k groups of shared buffers for storing the cells routed through the network for a period of time not greater than one cell cycle, where k is incremented from 1 to �log.sub.2 N/log.sub.2 .rho.!.sup.-1 and .rho. equals a predetermined speed-up factor. In one aspect of this embodiment, the number of shared buffers is simply equal to N/.rho.. To prevent cell contention and cell loss, all of the contentious cells (cells destined for the same output during the same cycle) are stored in the same shared buffer. Connected to the shared buffers are .rho..sup.k groups of (N/.rho..sup.k).times.(N/.rho..sup.k) routing networks each having a plurality of output ports for outputting the cells, stored in the shared buffers, based on the destination addresses of each cell. Due in part to the utilization of .rho..sup.k groups of shared buffers, a large reduction in both hardware costs and chip real estate is realized. Specifically, a decrease in the number of switching stages is achieved.

Distribution network switch for very large gigabit switching architecture

A method and system are disclosed for scheduling the assignment and writing of cells from cell sources into a outgoing bitstream transmitted from each device of an ATM communications network. The timeslots are organized into fixed length cycles which cycles each have a sequence of N timeslots, where N is an integer &gt;1. Furthermore, each cycle is divided into at least one round comprising a variable length subsequence of the timeslots of the cycle. During each timeslot of a uniform timeslot clock, at least one subset of the sources is identified. Each subset corresponds to a round. One cell from each subset is assigned to, and written into, a respective timeslot of the corresponding round. During each timeslot of the timeslot clock, each of the sources is assigned a priority state depending on how many cells of that source have been previously assigned to timeslots during the current cycle and whether or not that source has a cell available for assignment to a round during that timeslot. The highest priority state assigned to any source during each timeslot is identified. One of the cells of each source with the identified highest priority state are assigned to, and written into, a timeslot of a corresponding round, in a round-robin fashion, to form the subsequence of cells of that round.

Growing community of inventors

Hsinchu, Taiwan

Gin-Kou Ma