Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Stmicroelectronics International N.v.

Sgs-thomson Microelectronics S.a.

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (rousset) Sas

Gilles Troussel

Eric Benoit

Jean-Marie Permezel

Céline Mas

Jean-Raphaël Bezal

François Ravatin

Jérôme Bourgoin

Celine Lardeau

Nicolas Moeneclaey

Sergio Lecce

Philippe Maige

Nicolas Lebouleux

C&eacute;line Lardeau

Christophe Tourniol

The present disclosure relates to device including first and second terminals connected to a bus, third and fourth terminals connected to power supply and reference potentials. A first transistor and a first resistor are in series between the first terminal and a first diode connected to the third terminal. A second resistor, a second transistor and a second diode are in series between the first and fourth terminals. A third transistor and a third resistor are in series between the first diode and the second terminal. A fourth resistor, a fourth transistor and a third diode are in series between the second and fourth terminals. At each consecutive transmission of a dominant bit and of a recessive bit, a circuit sets the transistors at the ON state during a time period starting with the recessive bit.

Device for CAN bus

A driver circuit includes a supply node, a control node configured to receive a control signal, and an output node. An output transistor is coupled to the output node to provide the CAN bus drive signal via the current path through the output transistor. A current mirror is in a current line from the supply node to the output node through the output transistor. The current line includes an intermediate portion between the current mirror and the output transistor. The current mirror is configured to be switched, as a function of the control signal between a first, dominant mode, with the CAN bus drive signal applied to the output node via the output transistor, and a second, recessive mode, with the output transistor providing a high output impedance at the output node.

Driver circuit, corresponding system and method

A control device for a matrix plasma display screen has a row driver circuit capable of sequentially selecting the rows of the matrix and a column driver circuit, for each column of the matrix, with an individual column driver unit that has at least a first transistor of the MOS type capable of emitting, towards each column of a desired set of columns, a state change signal in order to allow the transition of the set from a first state towards a second state, and a controller. The first transistor is capable of emitting state change signals that have a state that is transitional from a low state towards a high state; the controller has a control transistor with one electrode directly connected to the power supply terminal and another electrode capable of delivering a control voltage to the control electrode of the first transistor, so as to limit the value of the current flowing through the first transistor in the course of the transitional state, in such a manner as to regulate the rise time of the state change signal.

Method and device for controlling a matrix plasma display screen

An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations.

Circuit for discharging an electrical load, power output stage comprising such a discharge circuit for the control of plasma display cells; and related system and method

The control of a plasma display panel, successively comprises, at least for all the cells of a current line having to switch state for the next line: a connection of a terminal of application of an intermediary supply voltage to output terminals of column control stages corresponding to the junction points of first and second switches between two terminals of application of a supply voltage, to perform a precharge or a predischarge of the screen cells; a disconnection of said output terminals from this intermediary voltage; and a connection of each output terminal to a first or to a second power supply voltage by the turning-on of the first or second switch of the corresponding stage, according to a luminance reference value, delayed with respect to the disconnection of the corresponding output terminal from the terminal of application of the intermediary voltage.

Control of a plasma display panel

Circuit for discharging an electrical load, power output stage comprising such a discharge circuit for the control of plasma display cells, and related system and method

A method and circuit to control of a circuit for addressing at least one line electrode of a plasma display panel having, for each line, a line selection stage formed of two switches in series between two input terminals of the selection stage, the method including use of a first one of the two switches of the selection stage of each line to flow a current from or to an inductive element of the addressing circuit.

Plasma display panel control circuit

A high-potential output stage includes an output circuit to power a load with a variable high potential when it receives a low-level active input logic signal. It also includes a driving circuit which produces a high-level control logic signal as a function of the input logic signal to drive the output circuit which is powered by a DC high potential. The output stage also synchronizes the input logic signal with variations of the variable high potential.

High-potential output stage

A voltage level shifting device includes an activation or deactivation control input, first and second output nodes, a capacitor coupled between the output nodes, a high-voltage transistor for charging the capacitor, a high-voltage transistor for discharging the capacitor, a comparator which generates a charge blocking signal and a discharge signal, and a control device which is operative to cause the charging transistor to be blocked when a charge blocking signal is generated and to turn on the discharging transistor upon receipt of a deactivation control signal and when a discharge signal is generated.

Voltage level shifting device

The invention concerns a drive circuit for a plasma panel consisting of cells arranged at the intersections of lines and columns, comprising, for each column of the panel, a column drive unit () for selecting the column by applying a voltage window, the column having a different capacitance (C) depending on whether or not the neighboring columns are selected, each drive unit () comprising first elements (T, C, CS) for changing the capacitance in a first predetermined time interval during the low-to-high transition of the voltage window, and second elements (T) for discharging said capacitance in a second predetermined time interval during the high-to-low transition of the voltage window, the second elements being controlled on the basis of an estimation of the capacitance obtained from data (Qi&#x2212;, Qi+) indicating whether or not the neighboring columns of said columns have been selected.

Control circuit drive circuit for a plasma panel

A method for controlling cells of a plasma screen of array type, formed of cells arranged at the intersections of lines and columns, including the step of sequentially applying to each line an activation potential and, during the activation of a line, applying an activation potential to selected columns, in which, while a line is activated, the selected columns are non-simultaneously activated.

Method and circuit for controlling a plasma panel

A driver circuit for driving a plasma display panel comprising a plurality of cells arranged in a matrix of lines and columns; comprising a set of driver output stages connected to line or column electrodes to which a first electrode of cells of a same line or a same column are connected, respectively. The driver circuit includes a detection device for detecting a short circuit between two or more of the outputs of the driver output stages. It allows to test for alignment faults in the flexible cable connecting together the driver module housing incorporating the driver circuit and the electrodes of the plasma display panel.

Driver circuit for driving a plasma display panel driver module incorporating said circuit and method of testing such a module

A method for testing output connections of at least one driver circuit that drives a plasma display panel. According to the method, at least one output of the driver circuit is switched to a high level for a predetermined time period. The output of the driver circuit is switched to a low level, and the time to discharge the output of the driver circuit with a constant discharge current is measured. It is determined whether a capacitive load is connected to the output of the driver circuit based on the measured time to discharge. In one preferred method, these steps are repeated for each of the outputs of the driver circuit. A driver circuit for driving a plasma display panel is also provided. The driver circuit includes driver output stages, and means for selectively sinking a constant discharge current from the output of at least one of the driver output stages to ground. Additionally, the driver circuit includes means for producing a measuring logic pulse whose duration is a function of a time required to discharge the output, and means for determining whether a capacitive load is connected to the output based on the measuring logic pulse.

Method and circuit for testing the output connections of a driver

The present invention relates to a power output stage for the control of plasma screen cells. It includes VDMOS-type N-channel charge and discharge transistors, the charge transistor being arranged to form a compound P-channel transistor. These transistors enable to issue a charge current to an output and to absorb a discharge current from this output. Two inverters are sized so that the potential of the control gate of the charge transistor drops more rapidly than the output potential when a discharge of this output is controlled. Thus, an output stage of limited bulk and without any risk of simultaneous conduction of the charge and discharge transistors is implemented.

Power output stage for the control of plasma screen cells

A device for correcting the linearity of ramps of a saw-tooth signal provided across a capacitor, charged by a first current source and periodically discharged at a desired frequency. The device modulates the charging current of the capacitor by a correction current to render the ramps of the signal not linear. In addition, the device includes circuitry to render the correction current proportional to the current provided by the first current source.

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Grenoble, France

Gilles Troussel