Cadence Design Systems, Inc.

C{dot Over (a)}dence Design System, Inc.

Gilles S C Lamant

Arnold Ginetti

Kenneth Ferguson

Randy Bishop

Rajan Arora

David J Mallon

Li-Chien Ting

Serena Chiang Caluya

Chia-Fu Chen

Roland Ruehl

Henry K Yu

Regis R Colwell

Min Cao

Bogdan George Arsintescu

Timothy Rosek

Simon Simonian

Alisa Yurovsky

Sravasti Gupta Nair

Jeff Taraldson

Kenneth Mackie

Min-Ching Lin

Johannes Franz Xaver Grad

Monika Bijoy

Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

Methods and systems for centering of pins during instance abutment

Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate adjustment of parameters of instances of programmable cells in the chain.

Methods and systems for customizable editing of completed chain of abutted instances

Disclosed herein are embodiments of an interactive design tool for designing electronic and photonic circuits, where features of the design may be displayed on the interactive layout GUIs as design objects. Design objects in a design database may include various types of design features, such as circuits, pins or ports, wires, and photonic waveguides. The design objects may be displayed on interactive layout GUIs according to the attribute data stored in the design database. The design objects may also be displayed according to a type of design feature represented by the design object. For example, the embodiments described herein may represent a 'port' as having a shape and size that comports with the eccentricities of both electrical and photonic designs. A port may be a hierarchical connection element in the database allowing the logical and physical connection between an instance and the geometries in the corresponding instance master.

Method for representing a photonic waveguide port and port specification

A system and method are provided for establishing an automated debugging environment in an Electronic Design Automation (EDA) work flow. A user interface is provided for interfacing with a user by displaying a list of debuggable parameters, accepting a selection thereof from a user, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user interface will be generated and provided to the user with a display of the relevant source code, callback function, parameter names and values, system state, and the like. Upon completion of the debugging process, the automatically-set breakpoint will be removed or modified to remove the automatically-set portion of the breakpoint.

Method and system for automatically establishing a component description format (CDF) debugging environment

In one aspect, a method for providing a circuit design includes defining an interconnect network comprising a plurality of wire connections, the defining performed after modification of the interconnect network and before completion of the interconnect network. An adjustment technique is applied to the wire connections of the defined interconnect network before completion of the interconnect network.

Automated adjustment of wire connections in computer-assisted design of circuits

Disclosed is a method and system for visualizing legal locations of edges and dimensions for an object being placed or edited in the layout. During the design process, visual indicators may be provided to the user to indicate the legal locations at which edges of an object may be placed in the layout. Gravitation and/or snapping may be provided automatically identify and/or move the edges to the legal locations. However, the user can control whether and under what circumstances the gravitation and/or snapping will occur. In this way, the designer does not need to manually place the edges of every single object, which is especially helpful for objects that are intended to have an edge at a legal location. Upon a design choice by the designer, the objects can be edited so that an edge does not need to immediately comply with a design rule.

Method and system for implementing an improved interface for designing electronic layouts

A system and method are provided for establishing a debugging environment in an Electronic Design Automation work-flow. A user-interface is provided for interfacing with users by displaying a list of debuggable parameters, accepting a selection thereof, and automatically locating both the callback function which sets the selected parameter, and the source code file which contains the callback function. Additionally, it is determined whether the callback function sets solely the selected parameter, or several different parameters, and an automatic breakpoint is set accordingly to break only responsive to the selected parameter. On execution of the modified callback function, execution will be arrested by the automatically-set intelligent breakpoint and a debugging user-interface will be generated for the user to display the relevant source code, callback function, parameter names and values, system state, and the like. Upon completion of the debugging process, the automatically-set breakpoint will be removed.

A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media.

Annotation management for hierarchical designs of integrated circuits

Disclosed are method(s), system(s), and article(s) of manufacture for implementing a layout of an electronic circuit using one or more constraint checking windows. The method identifies some constraints on multiple-patterning lithography and multiple constraint checking windows for the layout. The method determines one or more metrics for a constraint checking window or for a layout and assigns one or more shapes in the one or more constraint checking windows to their respective mask designs based on the one or more metrics. The method traverses through the one or more constraint checking windows until all shapes in the layout are assigned to their respective mask designs. The method may also determine a processing order for the one or more constraint checking windows based on the distribution of a type of shapes in the layout.

Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes

Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking.

Spine selection mode for layout editing

An improved approach to pcell caching is disclosed that enables safe and efficient multi-user access to pcell caches. Locking structures are used in conjunction with counters to provide multi-user support for pcell caches. When a modification occurs to cached pcell data, an update is made to the appropriate counter(s). The value(s) of the counters are checked to determine whether the item of data operated upon by an entity is still valid or if another concurrent entity has made changes to the data.

Method and system for implementing multiuser cached parameterized cells

The invention is directed to a method, computer program product and apparatus for a body of code to specify how database elements are combined to create a complex element, a database grouping is created that receives the content of the evaluation without introducing a level of hierarchy, and provides graphical user interface (GUI) to interactively manipulate the element.

Method and system for implementing stacked vias

Parameterized cells are cached and provided by the plug-in to increase the speed and efficiency of an application for circuit design. This allows source design to be read-interoperable and also enables some basic write-interoperability in the source design.

Method and system for implementing cached parameterized cells

An improved method and system are disclosed for utilizing abstracted versions of layout portions in conjunction with parameterized cells (pcells). One significant advantage is that abstracted versions of pcells can be generated from normal pcells and stored in a pcell cache, which avoids the need to abstract layout pcells on the fly.

Method and system for implementing abstract layout structures with parameterized cells

A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element.

Growing community of inventors

Sunnyvale, CA, United States of America

Gilles S C Lamant