Freescale Semiconductor,inc.

Nxp Usa, Inc.

Gilles Muller

Ronald J Syzdek

Karthik Ramanan

Jeffrey C Cunningham

Tahmina Akhter

Cheong Min Hong

Jon Scott Choy

Kerry A Ilgenstein

Jacob Williams

A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.

Split-gate memory having sector retirement with reduced current and method therefor

A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.

Common source architecture for split gate memory

The present disclosure provides for semiconductor structures and methods for making semiconductor structures. In one embodiment, isolation regions are formed in a substrate, and wells are formed between the isolation regions. The wells include a first low voltage well and a second low voltage well in a logic region of the substrate, and a memory array well in an NVM region of the substrate. A first layer of oxide is formed over the first low voltage well and the memory array well, and a second layer of oxide is formed over the second low voltage well, the second layer being thinner than the first layer. Gates are formed over the wells, including a first gate over the first low voltage well, a second gate over the second low voltage well, and a memory cell gate over the memory array well. Source/drain extension regions are formed around the gates.

Semiconductor memory cell and driver circuitry with gate oxide formed simultaneously

A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. The circuit stage includes a first output node and a second output node. The first output node is coupled via a current path to a first output of the level shifter and the second output node is coupled to via a current path to a second output of the level shifter. One of the diodes is coupled to the first output node and a power supply terminal. The other diode is coupled to the second output node and the power supply terminal.

Level shifter circuit

A circuit includes a non-volatile memory, a calibration circuit, and a sense amplifier. The sense amplifier senses a state of a memory cell during sensing. The sense amplifier includes a differential circuit having a first input coupled to a reference current source, a second input, and an output coupled to the calibration circuit during a calibration mode. A calibration current source is configured to be coupled to the second input of the differential current sensing circuit during the calibration mode and decoupled from the second input during the sensing mode. A variable current source is coupled to the differential current sensing circuit and the calibration circuit. The calibration circuit tests a plurality of currents of the variable current source during the calibration mode and selects one of the plurality of currents. The sense amplifier senses using the selected one of the plurality of currents.

Multibit sense amplifier calibration

An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Oscillator with startup circuitry

A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.

Control gate word line driver circuit for multigate memory

A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.

Compensated hysteresis circuit

A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump.

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Austin, TX, United States of America

Gilles Muller