Nxp USA, Inc.

Freescale Semiconductor,inc.

Nxp B.v.

Gilles Montoriol

Birama Goumballa

Cristian Pavao Moreira

Olivier Vincent Doare

Didier Salle

Dominique Delbecq

Stephane Damien Thuries

Hao Li

Antonius Johannes Matheus De Graauw

Hugues Beaulaton

Nishant Lakhera

Akhilesh Kumar Singh

Thierry Cassagnes

Pierre Pascal Savary

Jacques Trichet

Robert Gach

Christophe Landez

Navas Khan Oratti Kalandar

Trung Duong

Maarten Lont

Achal Venkatesh

Akbar Ghazinour

Stephane Dugalleix

Stephane Colomines

Philippe Riondet

Charaf-Eddine Souria

Stéphane Damien Thuries

Phillipe Riondet

Jaques Trichet

A power amplifier stage including multiple amplifier branch circuits, in which each amplifier branch circuit includes a cascode device, a source device, and a replica cascode device. The cascode device has current terminals coupled between an output node and an intermediate node, and has a control terminal receiving a corresponding activation signal. The source device has current terminals coupled between a supply reference node and the intermediate node, and has a control terminal receiving an input signal. The replica cascode device has current terminals coupled between a supply node and the intermediate node, and has a control terminal receiving a corresponding complementary activation signals. An output power level of the power amplifier stage is controlled by asserting a selected number of activation signals and corresponding complementary activation signals for activating a selected number of the amplifier branch circuits.

Current steering biasing for power control in cascode-based power amplifier stage of radar applications for improved reliability

A radar system includes a hybrid-power amplifier and a power control unit coupled to the hybrid-power amplifier. The power control unit is configured to control the amplification of a chirp signal output by the radar system based upon an assessment of an interchirp time provided by a chirp profile. The interchirp time is a time difference between a first chirp signal and a second chirp signal that are to be output by the hybrid-power amplifier. When the power control unit determines that the interchirp time is less than an interchirp time threshold, a fast-power loop control configuration is used to control the transmitted output power at hybrid amplifier level. When the power control unit determines that the interchirp time is equal to or greater than the interchirp time threshold, a slow-power loop configuration or a combination of the slow-loop configuration and the fast-loop configuration is used to control the transmitted output power at the hybrid-power amplifier. A look-up table generated by the power control unit in a controller is used to ascertain the control signals and values that are to be used by the hybrid-power amplifier and voltage regulator to amplify the chirp signal.

Power control for radar applications and method thereof

The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter. Example embodiments include a radar transceiver () having a normal mode of transmitter operation and a self-test mode of operation, the transceiver () comprising: a digital controller () configured to provide a digital control signal indicative of a phase shift; a digital to analogue converter () configured to receive the digital control signal and provide an analogue signal in accordance with the phase shift; a phase shifter () configured to receive the analogue signal and provide a phase shifted output signal for transmission; a dummy load () connected to receive the analogue signal from the digital to analogue converter () and to provide an analogue output; a resistor network () connected across an output of the dummy load (); a testing module () configured to measure the analogue output of the dummy load (); and a controller module () configured to control operation of the dummy load (), testing module () and digital controller () during the self-test mode of operation by: enabling the dummy load (); operating the digital controller () to provide a range of digital control signals to the digital to analogue converter (); and operate the testing module () to measure the analogue output of the dummy load () to determine a measure of linearity of the digital to analogue converter ().

Radar transceiver

Multi-channel radio frequency (RF) transmitter () and method of calibrating the transmitter are provided. In an embodiment, the method involves applying an intermediate frequency (IF) signal with different compensation values on a first phase rotator () in a first channel transmitter module (TX) of the transmitter, wherein the different compensation values are designed to compensate for a particular phase influencing factor, applying phase codes with the same different compensation values for different phases on a second phase rotator () in a second channel transmitter module (TX), measuring resultant phase errors due to phase errors of the first and second channel transmitter modules for the different compensation values, and based on the resultant phase errors, selecting one of the different compensation values to be used as a calibrated compensation value for the first and second phase rotators in the first and second channel transmitter modules to compensate for the particular phase influencing factor.

Phase rotator calibration of a multichannel radar transmitter

Embodiments are provided herein for a packaged semiconductor device and method of fabricating, the device including: a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and a support structure including an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.

Package with support structure

The disclosure relates to a phase shifter having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analog signal to provide a phase shifted signal, switching circuitry and a controller arranged to provide the analog signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

Phase shifter

A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value &#x3b8;, receive a second phase value &#x3b8;, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value &#x3b8;, and compute a second digital phase shift control value based on the received second phase value &#x3b8;. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.

Method and apparatus for generating phase shift control signals

An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.

Integrated circuit, radar device and method of calibrating a receiver

A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.

Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology

A charge pump circuit comprises a first bipolar transistor device and a second bipolar switching device arranged in a differential pair configuration. A first terminal of each of the first and second bipolar switching devices are coupled to a supply. A second like terminal of each of the first and second bipolar switching devices are coupled together and to ground potential via a pulsed current source. A field effect switching device is also provided and the first terminal of the first bipolar switching device is coupled to the voltage supply via the field effect switching device.

Charge pump circuit, phase locked loop apparatus, integrated circuit, and method of manufacture of a charge pump

An XOR phase detector for a phase-locked loop PLL comprises an XOR gate which has an input for a periodic reference signal and another input connected to a frequency divider of the PLL. A level shifter has a level shifter input connected to an output of the XOR gate and a level shifter output connectable to a voltage-controlled oscillator VCO of the PLL. The level shifter is connectable between low and high voltage providers and has a high level and a low level. The level shifter is arranged to deliver at its output the high level or the low level depending on whether the voltage at the output of the XOR phase detector is low or high. The level shifter further has a setpoint input for setting the high level to a setpoint level.

XOR phase detector, phase-locked loop, and method of operating a PLL

An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.

Integrated circuit device and method of dynamically modifying at least one characteristic within a digital to analogue converter module

An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

Integrated circuit comprising frequency generation circuitry for controlling a frequency source

An arrangement and method for impedance matching (e.g., for a power amplifier) comprising a first node () for receiving an output current to be impedance matched; a second node () for receiving output current from the first node; a first current conductor () for carrying current from the first node to the second node; a third node () for receiving output current from the second node; and a second current conductor () for carrying current from said second node to said third node, whereby the first and second current conductors are closely positioned so that their inductance is the sum of their self-inductances and the negative sum of their mutual inductance. The current conductors may be wire bonds, the arrangement may include a capacitor integrated in a power amplifier IC module, in which the capacitor may be provided in a separate IC from the power amplifier, the arrangement may utilize a plurality of impedance matching cells, and the wire bonds may be interdigitated across the semiconductor die. This provides the following advantages: easy to implement; increased accuracy of matching; requires few external components; easy to manufacture; no need for dedicated design flow; requires only standard IC production and test tools; uses low loss matching networks; involves only a small increase in die size (due to integration of capacitor), but the total size of the solution may be significantly reduced (e.g., by 50%) because of the reduced number of external components.

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Plaisance du Touch, France

Gilles Montoriol