Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Be Spoon

Thomson Composants Militaires Et Spatiaux

Gilles Masson

Laurent Ouvry

Francois Dehmas

Frédéric Hameau

Frederic Hameau

Jacques Reverdy

Mykhailo Zarudniev

Michaël Pelissier

Shanthi Sudalaiyandi

A UWB pulse emitter includes an H-bridge having first and second branches in parallel, a first end common to the branches being connected to a first amplitude control module to regulate a high voltage, a second end common to the branches being connected to a second amplitude control module to regulate a low voltage. A first envelope control module controls the shape of the positive portion of a UWB pulse and a second envelope control module controls the shape of the negative portion of this pulse. Each branch comprises first and second switches for respectively switching the high voltage to a first or second input of the first envelope control module and the low voltage to a first or second output of the second envelope control module. Centre taps of the branches, between which the UWB antenna is connected, connect the outputs and the inputs of the control modules.

Very-low-consumption reconfigurable-waveform compact UWB emitter

This electronic notch filter is able to receive an input signal and deliver a filtered signal having an amplitude, at a cut-off frequency, that is attenuated with respect to that of the input signal. It comprises a module for integrating the input signal during several successive time windows, each time window starting at a respective initial time instant and having a duration substantially equal to the inverse of the cut-off frequency, the initial temporal time instants of at least two distinct windows being separated by a temporal shift of a value greater than or equal to a predefined reference duration, each integration of the input signal during a respective temporal window resulting in a respective intermediate signal; and a module for summing the intermediate signals coming from the integration module; the filtered signal depending on the sum of said intermediate signals.

Notch filter with successive windowed integrations, related band-pass filtering device, frequency detection system and processing method

The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (B,B) coupled in series with each other, each comprising a lead portion () and a lag portion (), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter () configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF') and to generate a first control signal (DLEAD_:n]) for controlling said lead portions () or a second control signal (DLAG[:n]) for controlling said lag portions () based on the sign and magnitude of the phase difference.

Digital delay locked loop

An ultra-wideband pulse generator for radio communication with phase modulation at frequencies of multiple gigahertz comprises an oscillator formed by a pair of intersecting differential branches that have two outputs connected to an LC resonant load. The transmission of a UWB pulse is caused by the application of a supply current to the differential pair over a few nanoseconds. Two current-injecting branches are respectively connected to the outputs S and S'. The control of phase modulation consists in applying an injection current to a single branch to unbalance the differential pair at the start of the generation of the UWB pulse. Depending on the side from which the injection current is applied, the oscillation at the carrier frequency will initiate with one phase or an opposite phase.

Generator of phase-modulated UWB pulses

An ultra-wideband pulse generator, for radio communication at frequencies of 2 to 11 GHz comprises an oscillator providing an output signal at carrier frequency F0 followed by a radiofrequency switching transistor and a control circuit controlling the gate of the transistor to turn it on for duration T corresponding to the desired duration of a UWB pulse. The control circuit is arranged to successively apply, during the same UWB pulse, a first gate voltage turning the transistor on with first internal resistance value for a first part of duration T, a second gate voltage that turns the transistor on with second internal resistance value, different from the first, for a second part of duration T. These internal resistances cause the oscillation to be attenuated differently for duration T of the pulse, allowing the spectrum of the pulse to maintain it within the spectral templates imposed by the radio communication standards.

UWB pulse generator

A UWB impulse receiver including an RF stage followed by a baseband processing stage. The baseband processing stage includes a Rake filter including a plurality of time fingers, each finger including an integrator of the baseband signal during an acquisition window, a control module, and a detection module estimating the received symbols from the integration results. During a synchronization phase, the control module drives respective positions of the acquisition windows associated with the different fingers, to scan at a reception interval, the RF stage only operating, in a course of the synchronization phase, during the plurality of acquisition windows.

Intermittent UWB receiver

A method for determining arrival time of a UWB pulse at a receiver. When a pulse is modulated at an RF frequency, the receiver includes a quadrature demodulator, a first correlating stage for correlating the in-phase signal with the first and second signals of an orthogonal base on a time window and a second correlating stage for correlating the quadrature signal with the first and second signals of the orthogonal base on the same window, a phase estimator estimating the phase of the signal received in the orthogonal base from the correlation results of the first and/or second correlating stage(s), and a computing device determining the arrival time from the phase thus estimated.

Method for determining the arrival time of a UWB pulse and corresponding receiver

A pulsed multi-channel UWB receiver. The receiver includes a first stage translating a received signal into baseband or at an intermediate frequency, a second stage carrying out quadrature mixing on the in-phase and quadrature channels of the first stage, a third stage carrying out an integration on a time window of the signals from the second stage, and a fourth stage carrying out a combination of the integration results from the third stage to provide the real part and the imaginary part of the modulation symbol. The receiver is configurable according to the receiving channel and processing type selected.

Reconfigurable multi-channel UWB receiver

A UWB receiver with time drift correction. After a frequency translation by a quadrature demodulator, a pulsed UWB signal received is integrated on successive time windows, and then sampled. A phase shift estimator determines a phase difference between samples separated by a multiple of the sampling period approaching the period of the pulses of the signal. A controller deduces from this phase difference a time offset to be applied to integrators to synchronize the receiver on the signal received.

UWB receiver with time drift correction

An integrator circuit with multiple time window functions for carrying out a plurality of integration operations in parallel, each integration operation being carried out in a coherent manner over a sequence of time windows including at least one such window. The circuit includes a plurality of integration paths each corresponding to an integration operation. The integration paths share a same voltage/current converter and a same first switching mechanism for switching a signal to be integrated at an input of the converter, each integration path further including at least one integration capacitor mounted in counter-reaction to a functional amplifier and receiving a resulting current via a second switching mechanism for selecting the path.

Integrator circuit with multiple time window functions

The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.

Device for demodulating a signal containing information being conveyed by phase shift keying

A frequency doubler circuit includes first and second arrangements of switches connected to the positive and negative inputs of a comparator, respectively, and arranged in such a way that first and third voltages during the first phase of a reference clock signal and second and fourth voltages during a second phase opposite to the first phase are applied to the positive and negative inputs, where the first and second voltages and the third and fourth voltages are shifted with respect to each other at a half-period of the reference clock signal and the ratio between slopes of the voltages is fixed with respect to a selected current.

Frequency doubler device

In a symmetrical phase-lock loop (PLL) device, first (IP, IP) and second (IP, IP) pairs of switches are disposed between (i) first and second outputs of a symmetrical time/voltage conversion block and (ii) first and second inputs of a voltage processing block. In addition, third (IP, IP) and fourth (IP, IP) pairs of switches are disposed upstream of the first and second inputs of the phase comparator (PC). Control means control the opening/closing of the first to fourth pairs of switches, such that: (a) during a first phase (P), a first clock signal (Clkref) is connected to the first input of the comparator, a second clock signal (Clkdly) is connected to the second input of the comparator, the first output of the conversion block is connected to the second input of the processing clock and the second output of the conversion block is connected to the first input of the processing block; and (b) during a second phase (P), the first clock signal is connected to the second input of the comparator, the second clock signal is connected to the first input of the comparator, the first output of the conversion block is connected to the first input of the processing block and the second output of the conversion block is connected to the second input of the processing block, in order to compensate the static phase error.

Device for static phase error compensation in a phase-lock loop system with a symmetrical structure

A current source delivering a constant current despite sudden voltage fluctuations which may be applied on its output. This current source includes two branches in parallel, a generating branch and a reference branch. The output current is kept constant by keeping the potential difference across the terminals of the resistors in the generating branch constant, by using a differential amplifier. All the transistors are of the NPN type.

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Renage, France

Gilles Masson