International Business Machines Corporation

Other

Sony Computer Entertainment Inc.

Toshiba America Electronic Components, Inc.

Gilles Gervais

Sang Hoo Dhong

Brian King Flachs

Christopher Michael Abernathy

Kirk David Peterson

Stephen Douglas Weitzel

Tetsuji Tamura

Alain F Loiseau

Jonathan James DeMent

Makoto Aikawa

Iwao Takiguchi

Norman Jay Rohrer

Brad William Michael

Rolf Hilgendork

Charles Ray Johns

David William Boerstler

Jieming Qi

Eskinder Hailu

Mack Wayne Riley

Yosuke Muraki

James Nolan Hardage

Robert Walter Berry, Jr

Thomas G Koehler

Byron Lee Krauter

Kazuhiko Miki

Norbert Schumacher

Rolf B Hilgendorf

Ingemar Holm

Douglas Hooker Bradley

Helmut Kohler

Yoichi Nishino

James D Wagoner

Gerhard Zilles

Scott Raymond Cottier

John L Sinchak

David George Caffo

Herman Reyes

A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

Optimizing voltage on a power plane using a host control unit to control a networked voltage regulation module array

A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.

Reducing power requirements of a multiple core processor

Optimizing voltage on a power plane using a networked voltage regulation module array

Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.

Generating a worst case current waveform for testing of integrated circuit devices

Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamiclock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

Dynamic power management in an execution unit using pipeline wave flow control

A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

Voltage identifier sorting

A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

Method for controlling operation of microprocessor which performs duty cycle correction process

Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

Modifying a test pattern to control power supply noise

In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.

Method and apparatus for testing to determine minimum operating voltages in electronic devices

Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control

A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

System and method for sorting processors based on thermal design point

A method and an apparatus for performing a shift operation on an operand. The method and apparatus configures input lines to comprise a first part that includes the bits in order representing various shift amounts in a first direction and a second part that includes bits ordered representing various shift amounts in a second direction. The shift is then performed by selecting the appropriate bits from the input line to create the result.

Method and system for performing shift operations

A method and an apparatus for suppressing errors reported by an error check function of a circuit. The method and apparatus utilizes a shifter to provide an enablement bit for the error reporting. An error is reported only if the enablement bit is set such that it allows the error to be latched through the circuit.

Method and apparatus for performing error checking

A method and system for controlling a clock signal is provided. The clock signal is first stored in a storage device. An input representing a clock control signal is input into a first end of a plurality of interconnected memory storage circuits. An outputted clock signal is output from a second end of the plurality of interconnected memory storage circuits based on receipt of the pulse representing the clock control signal. In one embodiment, the plurality of interconnected memory storage circuits is comprised of latches. In an alternate embodiment, the plurality of interconnected memory storage circuits is comprised of latches and master/slave flip-flops.

Method and system for synchronously transferring data between clock domains sourced by the same clock

Growing community of inventors

Austin, TX, United States of America

Gilles Gervais