Infineon Technologies Ag

Gilles Delarozee

Dirk Ahlers

Thomas Stoek

Daniel Schleisser

Christopher Spielman

Ralf Otremba

Gerhard Noebauer

Teck Sim Lee

Markus Dinkel

Erwin Huber

Liu Chen

Lutz Goergens

Tien Lai Tan

Jia Yi Wong

Wei Han Koo

Marco Puerschel

Thomas Stoeck

A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package

A semiconductor package includes a leadframe, a first transistor chip connected to a first island of the leadframe in a drain-down configuration, and a second transistor chip connected to a second island of the leadframe in the same drain-down configuration as the first transistor chip. The first and the second islands of the leadframe are mutually electrically isolated from one another. The first island includes an extension which extends beyond a perimeter of the first transistor chip in a direction towards the second island and overlaps the second transistor chip. The first transistor chip and the second transistor chip are electrically interconnected with one another via the extension of the first island and a first electric connection element electrically connecting the extension to the second transistor chip to form a half bridge circuit.

Semiconductor package with leadframe

A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.

Transistor package with terminals coupled via chip carrier

A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Semiconductor module including semiconductor chips coupled to external contact elements

Growing community of inventors

Gruenwald, Germany

Gilles Delarozee