Lattice Semiconductor Corporation

Gilles Bosco

Om P Agrawal

Fabiano Fontana

Hua Xue

Harish Venkatappa

Issak Veytsman

Various techniques are provided to selectively collapse connections. In one example, a computer readable medium includes a computer program for performing a method of selectively collapsing connections between a plurality of LUTs. The method includes performing a first timing analysis to determine a timing slack value for each connection and determine a number of timing paths using each connection. The method also includes calculating a weight for each connection based on at least the timing slack value and the number of timing paths. The method further includes comparing the connections associated with a first one weight interval with collapsing criteria, wherein the first weight interval includes weights larger than weights of the remaining weight intervals. The method also includes collapsing the connections associated with the first weight interval that satisfy the collapsing criteria, and selectively repeating the comparing and collapsing for connections associated with remaining weight intervals.

Weight based look up table collapsing for programmable logic devices

An algorithm is disclosed to partition input variables between a feeder logic block and a receiver logic block. For a given input variable partition, the algorithm assigns both a cost to the number of product terms cascaded from the feeder logic block to the receiver logic block as well as a cost that increases as the number of input variables assigned to the receiver logic block approaches its maximum input width. The costs for a variety of input variable partitions are tested to determine an optimal input variable partition.

Algorithm to increase logic input width by cascading product terms

Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., &#x2266;80PTs) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation

Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage- wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., &gE;80 PT's) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps-of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

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Gilles Bosco