Altera Corporation

Cadence Design Systems, Inc.

Giles V Powell

Andy Louie Lee

Thomas Henry White

Christopher F Lane

Paul Leventis

Brian D Johnson

Roland Ruehl

Karun Sharma

Bradley Jensen

Alexandre Arkhipov

Wuu-Cherng Lin

Dustin Do

Swee Aun Lau

Bruce B Pedersen

Chiakang Sung

Rakesh H Patel

Cameron R McClintock

Wayne Yeung

David Lewis

David Edward Jefferson

David Cashman

Ketan H Zaveri

Hyun Mo Yi

Vikram Santurkar

Triet M Nguyen

Michael Chan

Jeffrey Tyhach

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

N-well/P-well strap structures

Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs

Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one shape of the shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while automatically satisfying one or more design rules, and perform one or more post-layout operations on the layout including the one or more parallel fill shapes.

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs

Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.

Integrated circuit floorplans

An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.

Distributing power with through-silicon-vias

A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Programmable logic device with redundant circuitry

A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be 'partial' and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

Use of dangling partial lines for interfacing in a PLD

Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.

Efficient arrangement of interconnection resources on programmable logic devices

A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be &ldquo;partial&rdquo; and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.

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Alameda, CA, United States of America

Giles V Powell