International Business Machines Corporation

Mcdata Corporation

Giles R Frazier

Michael K Gschwind

Robert J Dugan

Christian Jacobi

Chung-Lung K Shum

Brian William Thompto

Anthony Saporito

Younes Manton

Gregory Francis Pfister

Karl Michael Taylor

William J Rooney

John R Flanagan

Naresh Nayar

Thomas M Brey

Jonathan D Bradbury

Louis William Ricci

Venkat Rajeev Indukuru

Matthew J Kalos

Daniel Gene Eisenhauer

Richard Louis Arndt

Ronald P Hall

Catherine C Huang

Harry M Yudenfriend

Hung Qui Le

Steven Mark Thurber

Daniel Francis Casper

Bruce Gerard Mealey

Jaya Srikrishnan

Cathy May

Frank William Brice

Brian Robert Mestan

Joseph C Elliott

Ingo Adlung

Kenneth M Trowell

Stefan Mueller

Renato John Recio

Roger Gregory Hathorn

Danny Marvin Neal

Jose Eduardo Moreira

David S Levitan

Bradly George Frey

Michael D Snyder

Mauricio J Serrano

James Xenidis

Gerhard Banzhaf

Gary L Whisenhunt

Paul Mackerras

Joran S C Siu

Kumar K Gala

Becky Bruce

Dono Van-Mierop

Bruce Mealy

Timothy John Slegel

Silvia Melitta Mueller

David F Craddock

William Joseph Armstrong

Brent Cameron Beardsley

Richard Loise Arndt

Alexander Erik Mericas

Gregory Scott Still

James P Allen

Michael Joseph Corrigan

Allan Samuel Meritt

Tan Lu

Suresh Eswara Warrier

Michael E O'Donnell

John Thomas O'Quin, Ii

Robert G Kovacs

William Miller

Kenneth J Fredericks

Christopher Francois

Zhong Liang Wang

John Fred Spannaus

Timothy R Marchini

Satya Prakesh Sharma

Gary Yuh Tsao

Maria Lorena Pesantez

David Henry Wilde

Gerhard Banzahf

A computing device and a method of allocating vector register files in a simultaneously-multithreaded (SMT) processor core are provided. A request for a first number (M) of vector register files is received from a borrower thread of the processor core. One or more available donor threads of the processor core are identified. A second number (N) of the vector register files, of the identified one or more available donor threads, are assigned to the borrower thread, where N is &#x2264;M. The borrower thread is parameterized to create a virtualized vector register file for the borrower thread, based on a width of the N vector register files of the identified one or more donor threads.

SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register files

Techniques for an extended prefix including a routing bit for an extended instruction format are described herein. An aspect includes generating, by an instruction preprocessing module, a first extended instruction corresponding to an internal operation including a first routing bit. Another aspect includes generating, by the instruction preprocessing module, a second extended instruction corresponding to a prefixed instruction set architecture (ISA) instruction including a second routing bit, wherein a value of the second routing bit is opposite a value of the first routing bit. Another aspect includes providing the first extended instruction and the second extended instruction to a central processing unit (CPU). Another aspect includes, based on the value of the first routing bit, routing the internal operation directly to an execution unit of the CPU, and based on the value of the second routing bit, routing the prefixed ISA instruction to a decode/execute path of the CPU.

Extended prefix including routing bit for extended instruction format

A method, computer program product, and system performing a method that include a processor defining a code fingerprint by obtaining parameters describing at least one of an event type or an event. The code fingerprint includes a first sequence. The processor loads the code fingerprint into a register accessible to the processor. Concurrent with executing a program, the processor obtains the code fingerprint from the register and identifies the code fingerprint in the program by comparing a second sequence in the program to the first sequence. Based on identifying the code fingerprint in the program, the processor alerts a runtime environment where the program is executing.

Configurable code fingerprint

A method and apparatus for garbage collection is disclosed herein. The method includes performing a garbage collection process without pausing execution of a runtime environment. The method also includes executing a first CPU instruction to load a first pointer that points to a first location in a first region of memory, where the first region of memory is undergoing garbage collection. The method also includes moving a first object pointed to by the first pointer from the first location in memory to a second location in memory.

Multi-section garbage collection

A method and apparatus for garbage collection is disclosed herein. The method includes specifying a load-monitored region within a memory managed by a run-time environment, enabling a load-monitored event-based branch configured to occur responsive to executing a first type of CPU instruction to load a pointer that points to a first location in the load-monitored region, performing a garbage collection process in background without pausing executing in the run-time environment, executing a CPU instruction of the first type to load a pointer that points to the first location in the load-monitored region, and responsive to triggering a load-monitored event-based branch, moving an object pointed to by the pointer with a handler from the first location in memory to a second location in memory.

Multi-section garbage collection method

Addressability of instructions and the addressing of data ranges are extended. One or more operands obtained from fields explicitly specified by an instruction are overridden (i.e., ignored), and instead, an address based on the instruction (e.g., an instruction address) is substituted for the one or more operands. This provides an address having more bits than allowed by the operand being overridden, thereby extending addressability of the instruction and extended data range addressing. Further, in one aspect, additional bits may be added to one or more immediate fields of the instruction, thereby extending addressability of the instructions and extending data range addressing.

Extending data range addressing

Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.

Converting multiple instructions into a single combined instruction with an extension opcode

Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.

Configurable interrupts for allowing an application to independently handle interrupts

Computer readable medium and apparatus for translating a sequence of instructions is disclosed herein. In one embodiment, an operation includes recognizing a candidate multi-instruction sequence, determining that the multi-instruction sequence corresponds to a single instruction, and executing the multi-instruction sequence by executing the single instruction.

Processor instruction sequence translation

The embodiments relate to a computer system, computer program product and method for managing a garbage collection process. Processing control is obtained based on execution of a load instruction and a determination that an object pointer to be loaded indicates a location within a selected portion of memory undergoing a garbage collection process. The determination includes identifying a base address and size of a first memory block subject to the garbage collection, and assigning a binary value to each first memory block section. An image of the load instruction is obtained and a pointer address is calculated from the image. It is determined whether the object pointer is to be modified. The object pointer is modified and stored in a selected location.

Method for translating a sequence of instructions is disclosed herein. In one embodiment, the method includes recognizing a candidate multi-instruction sequence, determining that the multi-instruction sequence corresponds to a single instruction, and executing the multi-instruction sequence by executing the single instruction.

Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core

Growing community of inventors

Austin, TX, United States of America

Giles R Frazier