Nxp B.v.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Gilberto Curatola

Youri Victorovitch Ponomarev

Matthias Merz

Georgios Vellianitis

Romano Hoofman

Nader Akil

Sebastien Nuttinck

Kyriaki Fotopoulou

Gerben Doornbos

Roel Daamen

Johannes Josephus Theodorus Marinus Donkers

Radu Surdeanu

Anco Heringa

Remco Henricus Wilhelmus Pijnenburg

Jan Willem Slotboom

Aurelie Humbert

Hans Mertens

Godefridus A M Hurkx

Prabhat Agarwal

Victor Zieren

Dusan Golubovic

Guillaume Boccardi

Marcus J H Van Dal

Fotopoulou Kyriaki

Anton Tombeur

A container for containing a perishable substance has a container wall with an inner side and an outer side. The wall has an electrically conductive layer extending between the inner side and the outer side. The inner side faces the space containing the substance. The container comprises electronic circuitry having a sensor for sensing a physical property or condition of the substance, and an antenna for communicating an RF signal to a receiver, external to the container. The RF signal is indicative of the physical property or condition sensed. The sensor is positioned so as to be exposed to the space containing the substance in operational use of the container. The antenna is positioned at the outer side, or between the outer side and the electrically conductive layer, and is electrically isolated from the electrically conductive layer.

Food package with integrated RFID-tag and sensor

An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Integrated circuit

A detector device comprises a substrate (), a source region (S) and a drain region (D), and a channel region () between the source and drain regions. A nanopore () passes through the channel region, and connects fluid chambers () on opposite sides of the substrate. A voltage bias is provided between the fluid chambers, the source and drain regions and a charge flow between the source and drain regions is sensed. The device uses a nanopore for the confinement of a sample under test (for example nucleotides) close to a sensor. The size of the sensor can be made similar to the spacing of adjacent nucleotides in a DNA strand. In this way, the disadvantages of PCR based techniques for DNA sequencing are avoided, and single nucleotide resolution can be attained.

Apparatus and method for molecule detection using nanopores

A tunnel field effect transistor and a method of making the same. The transistor includes a semiconductor substrate. The transistor also includes a gate located on a major surface of the substrate. The transistor further includes a drain of a first conductivity type. The transistor also includes a source of a second conductivity type extending beneath the gate. The source is separated from the gate by a channel region and a gate dielectric. The transistor is operable to allow charge carrier tunnelling from an inversion layer through an upper surface of the source.

Tunnel field effect transistor

A device is provided that includes a battery layer on a substrate, where a first battery cell is formed in the battery layer. The first battery cell includes a first anode, a first cathode, and a first electrolyte arranged between the first anode and the first cathode, where the first anode, the first cathode, and the first electrolyte are arranged in the battery layer such that perpendicular projections onto the substrate of each of the first anode and the first cathode are non-overlapping. A method of manufacturing such device is also provided. A system is also provide that includes such device for supplying power to an electronic device.

Stacked multi-cell battery concept

A charge-pump circuit a plurality of transistor stages connected in series between a supply voltage input node and a boosted voltage output node, wherein at least one transistor stage comprises a multiple-gate transistor, which transistor comprises at least two gates, of which one is a first gate for switching the transistor on or off according to a voltage applied to the first gate, and one is an additional second gate for controlling the threshold voltage of the multiple-gate transistor, independently of the first gate, according to a control voltage applied to the second gate.

Charge-pump circuit

The invention relates to a method of determining a charged particle concentration in an analyte (), the method comprising steps of: i) determining at least two measurement points of a surface-potential versus interface-temperature curve (c, c, c, c), wherein the interface temperature is obtained from a temperature difference between a first interface between a first ion-sensitive dielectric (Fsd) and the analyte () and a second interface between a second ion-sensitive dielectric (Ssd) and the analyte (), and wherein the surface-potential is obtained from a potential difference between a first electrode (Fe) and a second electrode (Se) onto which said first ion-sensitive dielectric (Fsd) and said second ion-sensitive dielectric (Ssd) are respectively provided, And ii) calculating the charged particle concentration from locations of the at least two measurement points of said curve (c, c, c, c). This method, which still is a potentiometric electrochemical measurement, exploits the temperature dependency of a surface-potential of an ion-sensitive dielectric in an analyte. The invention further provides an electrochemical sensor for determining a charged particle concentration in an analyte. The invention also provides various sensors which can be used to determine the charged particle concentration, i.e. EGFET's and EIS capacitors.

Electrochemical potentiometric sensing without reference electrode

A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells () for forming CMOS devices and second wells () for forming Schottky devices. Then, transistors are formed in the first wells, the second wells protected with a protection layer () and suicide contacts () formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material () and each second well ().

Schottky diode and method of manufacture

A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.

Field-effect magnetic sensor

A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate () using a patterned hard mask () covering the higher steps of said profile; forming a gate stack () against the side wall of the higher step; forming spacers () on either side of the gate stack (); and implanting a first type impurity () in the higher step and an opposite type impurity in the neighboring lower step (), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (). In a preferred embodiment, the method further comprises forming a sacrificial spacer () against a side wall of a higher step and the side wall of the hard mask (); further etching the lower step () next to said spacer () and subsequently growing a further semiconductor portion () on said lower step and removing the spacer () prior to forming the gate stack. Further disclosed is an IC comprising tunnel transistors manufactured in accordance with this method.

Method of manufacturing a tunnel transistor and IC comprising the same

A transistor device (), the transistor device () comprising a substrate (), a fin (A) aligned along a horizontal direction on the substrate (), a first source/drain region () of a first type of conductivity in the fin (A), a second source/drain region () of a second type of conductivity in the fin (A), wherein the first type of conductivity differs from the second type of conductivity, a channel region () in the fin (A) between the first source/drain region () and the second source/drain region (), a gate insulator () on the channel region (), and a gate structure () on the gate insulator (), wherein the sequence of the first source/drain region (), the channel region () and the second source/drain region () is aligned along the horizontal direction.

Transistor device and method of manufacturing such a transistor device

An impact ionization MOSFET is formed with the offset from the gate to one of the source/drain regions disposed vertically within the device structure rather than horizontally. The semiconductor device comprises a first source/drain region having a first doping level; a second source/drain region having a second doping level and of opposite dopant type to the first source/drain region, the first and second source/drain regions being laterally separated by a silicon-germanium intermediate region having a doping level less than either of the first and second doping levels; a gate electrode electrically insulated from, and disposed over, the intermediate region, the first and second source/drain regions being laterally aligned with the gate electrode; where the entire portion of the first source/drain region that forms a boundary with the intermediate region is separated vertically from the top of the intermediate region.

Self-aligned impact-ionization field effect transistor

A method of making a FET includes forming a gate structure (), then etching cavities on either side. A SiGe layer () is then deposited on the substrate () in the cavities, followed by an Si layer (). A selective etch is then carried out to etch away the SiGe () except for a part of the layer under the gate structure (), and oxide () is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide () can reduce junction leakage current.

Field effect transistor structure with an insulating layer at the junction

A tunnel transistor includes source diffusion () of opposite conductivity type to a drain diffusion () so that a depletion layer is formed between source and drain diffusions in a lower doped region (). An insulated gate () controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer () which is made of a different material to the lower layer () and cap layer ().

Growing community of inventors

Korbek-lo, Belgium

Gilberto Curatola