Intel Corporation

Digital Equipment Corporation

Other

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Gilbert M Wolrich

Vinodh Gopal

Wajdi K Feghali

James D Guilford

Kirk S Yap

Debra Bernstein

Matthew James Adiletta

Erdinc Ozturk

Martin Guy Dixon

Sean M Gulley

Mark B Rosenbluth

Daniel Cutter

William Ralph Wheeler

Donald F Hooper

Sanjeev Jain

Sean Mirkes

Bret L Toll

Mark C Davis

Alexandre J Farcy

Bradley A Burres

Maxim Loktyukhin

Christopher Dolan

Jaroslaw Sydir

Myles Wilde

Kamal J Koshy

Gunnar Gaubatz

Shay Gueron

William C Hasenplaugh

Hugh M Wilkinson, Iii

Timothy C Fischer

Christopher F Clark

Robert P Ottavi

Andrew S Olesin

Hugh Wilkinson

Edward J McLellan

Kahraman D Akdemir

Deniz Karakoyunlu

John A Kowaleski

John J Ellis

Sribalan Santhanam

John Cyr

James Redfield

Robert A Yodlowski

Matthew C Merten

Sridhar Lakshmanamurthy

Michael F Fallon

Mark D Matson

Chen-Chi Kuo

Tong Li

Yogesh Bansal

David Romano

Matthew I Adiletta

Makaram Raghunandan

John D Clouser

Richard Guerin

Bhavin Shah

Erdine Ozturk

Nital Patwa

Era Nangia

Samuel Ho

Sanu K Mathew

Michael E Kounavis

Sudhir K Satpathy

James R Lundberg

Srinivas Chennupaty

Aaron Gorius

Robert S Chappell

Brent Ralph Boswell

Jose Niell

Tracy Garrett Drysdale

John Wishneusky

Daniel W Dobberpuhl

Anil K Jain

Stephanie L Hirnak

Robert J Kushlis

James T Kukunas

John J Vranich

Chang-Ming P Lin

Matt Bace

Prashant Paliwal

Thomas L Dmukauskas

Jon Krueger

James P Ellis

John A Kowaleski, Jr

James D Gulilford

Roy W Badeau

David Deverell

Bret T Toll, I

Schuyler Eldridge

Jim D Guilford

Kaan Yuksel

Waidi K Feghali

Chandra Vora

Douglass Carrigan

Vindoh Gopal

Maxim Loktyukin

John Sweeney

Natarajan Rohit

Wadji K Feghali

Selcuk Baktir

Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Rotate instructions that complete execution either without writing or reading flags

Instructions and logic to provide SIMD SM4 cryptographic block cipher

An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

Apparatus and method for executing Boolean functions via forming indexes to an immediate value from source register bits

A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Method and apparatus to process SHA-2 secure hashing algorithm

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Addition instructions with independent carry chains

A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a, b, e, and ffor a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements a, b, c, d, e, f, g, hof the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements a, b, e, and fthat have been updated from the corresponding state data elements a, b, e, and fby at least one round of the SHA2 hash algorithm.

Instructions processors, methods, and systems to process secure hash algorithms

A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

Method and apparatus to process KECCAK secure hashing algorithm

Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

Instruction and logic to provide SIMD secure hashing round slice functionality

Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Growing community of inventors

Framingham, MA, United States of America

Gilbert M Wolrich