Texas Instruments Corporation

Texas Instruments France

Gilbert Laurenti

Karim Djafarian

Herve Catan

Vincent Gillet

Mark L Buser

Marc Couvrat

Jean-Pierre Giacalone

Shigeshi Abiko

Yves Masse

Gael Clave

Alain Boyadjian

Emmanuel Ego

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Laurent Ichard

Gary A Cooper

Douglas E Deao

Lee Alan Larson

Eric L Badi

Armelle Laine

Francois Theodorou

Jean-Marc Philippe Bachot

Anne Lombardot

Jean-Louis Tardieux

Dario Cardini

Frederic Nidegger

David Russell

N M Ganesh

Ganesh M Nandyal

Olivier Morchipont

A program is executed on a processor to produce execution events. The execution events are traced using a first trace mode during a first portion of the program execution, wherein a portion of trace information for the execution events is omitted from a trace report while tracing in the first trace mode. The mode of tracing is dynamically changed to a second trace mode in response to an event trigger, such that all execution events that occur during the change of mode are captured. Execution events are traced during a second portion of the program execution using the second trace mode, wherein additional trace information for the execution events is included in the trace report while tracing in the second trace mode. The trace mode may be dynamically switched between the two trace modes during execution of the program.

Recording processor instruction execution cycle and non-cycle count trace events

In a method for tracing data within an integrated circuit, a default time stamp granularity is selected for a sequence of time stamps, wherein each time stamp has a resolution of 2**N. A sequence of trace events is captured and an elapsed time is determined between each time sequential pair of trace events in the sequence of trace events. A time stamp is formed to associate with each trace event of the sequence of trace events, wherein each time stamp has an associated time stamp granularity, wherein the time stamp has the default time stamp granularity if the elapsed time between a current trace event and a sequentially prior trace event is less than 2**N time slots, otherwise the time stamp granularity is slid to a larger value such that the elapsed time can be represented by N bits, whereby a small number N of bits can accurately represent a large range of elapsed times.

Sliding granularity time stamping

In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.

Power management events profiling

A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Dynamic frequency scaling for JTAG communication

A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the content of the repeat count register, and to modify the content of the repeat count register. The repeat instruction comprises two parts, the first of which initializes the repeat count index register and initiates repeat of a subsequent instruction, and the second part of which modifies the content of the repeat count register.

Processor with a computer repeat instruction

A processor is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A coefficient data pointer is provided for accessing coefficient data for use in a multiply-accumulate (MAC) unit. Monitoring circuitry determines when the coefficient data pointer is modified (step ). When an instruction is executed (step ) that requires a coefficient datum from memory in accordance with the coefficient data pointer, a memory access is inhibited (step ) if the coefficient data pointer has not been modified since the last time a memory fetch was made in accordance with the coefficient data pointer and the previously fetched coefficient datum is reused. However, if the coefficient data pointer was modified since the last time a memory fetch was made in accordance with the coefficient data pointer, then the required coefficient datum is fetched from memory (step ). A shadow register within the MAC unit execution pipeline temporarily saves coefficient data for possible reuse.

Processor with pointer tracking to eliminate redundant memory fetches

A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.

Microprocessor with selected partitions disabled during block repeat

An execution unit for a processing engine comprising first head part circuitry for deriving an intermediate signal from an input signal. The execution unit also comprises further circuitry which receives the intermediate signal and operates on it to produce a final signal. The further circuitry is typically configured to perform one or more signal processing functions in combination with the first circuitry, and generally comprises separate circuitry for each function. The intermediate signal is configured to be usable by each of the separate circuitry.

Bit field processor

A processing engine for executing instructions in parallel comprises an instruction buffer for holding at least two instructions, with the first instruction in a first position and the second instruction in a second position. A first decoder provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position. Arbitration and merge logic is provided for arbitrating between the first and second control signals and for merging the first and second control signals for controlling power of execution of the instructions in accordance with a set of parallelism rules. A conditional execution unit is responsive to false condition signals from the arbitration and merge logic to inhibit or modify the effect of the control signals. The parallelism rules provide for efficient instruction execution, and the avoidance of resource conflicts.

Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution

A processing engine includes an instruction buffer operable to buffer single and compound instructions pending execution. A decode mechanism is configured to decode instructions from the instruction buffer. The decode mechanism is arranged to respond to a predetermined tag in a tag field of an instruction, which predetermined tag is representative of the instruction being a compound instruction formed from separate programmed memory instructions. The decode mechanism is operable in response to the predetermined tag to decode at least first data flow control for a first programmed instruction and second data flow control for a second programmed instruction. The use of compound instructions enables effective use of the bandwidth available within the processing engine. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. A compound address field of the predetermined compound instruction can be arranged at the same bit positions as the address field for a hard compound memory instruction, that is a compound instruction which is programmed. In this case the decoding of the addresses can be started before the operation code of the instructions have been decoded. To reduce the number of bits in the compound instruction, addressing can be restricted to indirect addressing and the operation codes for at least the first instruction can be reduced in size. In this way, the compound instruction can be arranged to have the same number of bits in total as the sum of the bits of the separate programmed instructions.

Dual access instruction and compound memory access instruction with compatible address fields

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

A processor ( ) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region ( ) is used to pass variables to a subroutine and to hold values representative of a first portion of a program counter ( ). A system stack region ( ) is used to hold values representative of a remaining portion of the program counter ( ) and to hold additional context information. The user stack region and the system stack region are managed independently so that software from a prior generation processor can be translated to run on processor ( ).

Stack Pointer Management

Linear vector computation

A processor ( ) is provided that is a programmable digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Instructions may be executed during delay slots after program branching while an execution pipeline is being restarted. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. A software breakpoint instruction is provided for debugging purposes. In order to correctly emulate the operation of the instruction pipeline when a software breakpoint instruction is executed during a delay slot, the width ( ) of the software breakpoint is the same as the replaced instruction. A limited number of breakpoint instruction length formats ( ) are combined with non-operational instructions (NOP, NOP ) to form a large number of combination instructions that match any instruction length format.

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Saint Paul de Vence, France

Gilbert Laurenti