At&t Bell Laboratories

Bell Telephone Laboratories

Gilbert L Mowery, Jr

Kevin D Kolwicz

Jack K Keller

The present invention relates to a glitch lockout circuit for a static random access memory (RAM) which prevents the writing or reading of incorrect data when a system clock is switched from a standard clock source to an alternate clock source. A dummy bit line is added to the memory arrangement which is always precharged during a first clock phase and discharged during a second clock phase. The state of the dummy bit line is latched with the first clock phase and is fed back to the clock generator to control the initiation of the second clock phase. Thus, if the dummy bit line stays low, the second clock phase will stay low and none of the RAM cells will be accessed.

Glitch lockout circuit for memory array

A first MOS (metal-oxide-semiconductor) NOR-gate device feeding a second MOS NOR-gate device feeding an MOS output load device is arranged to yield a three output level buffer circuit, that is, whose output to a common data bus line can be 'high' ('1'), 'low' ('0'), or of very high impedance ('floating'). Each NOR-gate contains a low .beta. ('load') depletion mode type of MOS transistor and a high .beta. ('driver') enhancement mode type of MOS; the output load device contains an output driver enhancement mode type of MOS transistor and an output load MOS transistor having a threshold intermediate that of the depletion mode and enhancement mode type of MOS transistor. In this manner, only a single voltage source V.sub.DD, or typically about +5 volts in N-MOS integrated circuit technology is required to power the buffer circuit completely.

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Allentown, PA, United States of America

Gilbert L Mowery, Jr