Qualcomm Incorporated

Other

Gilbert Christopher Sih

Qiuzhen Zou

Inyup Kang

Raghu Narayan Challa

Avneesh Agrawal

Haitao Zhang

Way-Shing Lee

De Dzwo Hsu

Shimman Arvind Patel

Brian K Butler

Farrokh Abrishamkar

Matthew Levi Severson

Tao Li

Brett Christopher Walker

Paul E Peterzell

Christian Holenstein

Anthony P Mauro

Arun Raghupathy

Jian Lin

Charles E Sakamaki

Li Feng Zhang

Edward George Tiedemann, Jr

Andrew P Dejaco

William Robert Gardner

Thunyachate Ekvetchavit

Jian Wei

Johnny Kallacheril John

Deepu John

Xufeng Chen

Richard Higgins

Ian J Fevrier

Quaeed Motiwala

Brian Clarke Banister

Stein Arne Lundby

Ning Bi

Franklin Peter Antonio

Paul Eric Jacobs

Lindsay A Weaver, Jr

Roland Reinhard Rick

Samir Kumar Gupta

Serguei A Glazko

Christopher Patrick

Chienchung Chang

Sanjay K Jha

Thomas Wilborn

Anthony Patrick Mauro, Ii

Mark Roh

S Katherine Lam

King-Chung Lai

Brian Scott Edmonston

Yushi Tian

Hemant Kumar

Prashant A Kantak

Andrew K Kan

Ziad Mansour

Quizhen Zou

De D Hsu

Injup Kang

A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Direct conversion receiver architecture

A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.

Cached memory system and cache controller for embedded digital signal processor

The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location on a subscriber unit in a terrestrial wireless telephone system using a set of satellites each transmitting a signal, the terrestrial wireless telephone system having base stations, including the steps of transmitting an aiding message from the base station to the subscriber unit, said aiding message containing information regarding a data boundary for each signal from the set of satellites, applying correlation codes to each signal yielding corresponding correlation data and accumulating said correlation data over an first interval preceding a corresponding data boundary yielding a first accumulation result, and a second interval following said corresponding data boundary yielding a second accumulation result.

Data boundary aware base station assisted position location

This disclosure describes video encoding techniques capable of reducing the number of processing cycles and memory transfers necessary to encode a video sequence. In this manner, the disclosed video encoding techniques may increase video encoding speed and reduce power consumption. In general, the video encoding techniques make use of a candidate memory that stores video blocks in columns corresponding to a search space for a motion estimation routine. A memory control unit addresses the candidate memory to retrieve multiple pixels in parallel for simultaneous comparison to pixels in a video block to be encoded, e.g., using Sum of Absolute Difference (SAD) or Sum of Squared Difference (SSD) techniques. A difference processor performs the parallel calculations. In addition, for subsequent video blocks to be encoded, the candidate memory can be incrementally updated by loading a new column of video blocks, rather than reloading the entire search space.

Video encoding and decoding techniques

DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU configuration, a single-MAC/dual-ALU configuration, or a dual-MAC/dual-ALU configuration. This flexibility allows the DSP to handle various types of signal processing operations and improves utilization of the available hardware. The DSP architectures further includes pipeline registers that break up critical paths and allow operations at a higher clock speed for greater throughput.

Digital signal processors with configurable dual-MAC and dual-ALU

A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.

Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length

The velocity of a wireless communications device (WCD) () is estimated. In response to this estimate a power control command rate is determined. The WCDtransmits power control signals to a base station () according to the power control command rate. The power control command rate may be determined by mapping the estimated velocity to a velocity range, and selecting a rate that corresponds to the velocity range as the power control command rate. Velocity is estimated by measuring a level crossing rate of a multipath signal.

Velocity responsive power control

This disclosure is directed to techniques for estimating signal-to-noise ratio (SNR) of signals received by a wireless communication device. The techniques take advantage of spatial receive diversity in a wireless communication device to achieve accurate estimates of SNR. In general, a spatial projection wiener filter function can be applied to incoming symbol estimates to support efficient computation of SNR. The estimated SNR can be used to produce power control commands for use in forward power control.

Signal-to-noise estimation in wireless communication devices with receive diversity

The velocity of a wireless communications device (WCD) is estimated. In response to this estimated velocity, a tracking speed of a filter is determined that corresponds to the estimated velocity. The filter filters a timing error signal to produce a control signal that controls the timing of a synchronization clock. This synchronization clock may be a finger clock that controls the timing of a pseudonoise (PN) sequence generator configured for despreading a pilot symbol sequence.

Velocity responsive time tracking

In general, the invention is directed toward a device for processing digital video data, such as an encoder, a decoder or an encoder/decoder (CODEC). The device makes use of an innovative architecture in which functionality is partitioned between an embedded processor, a digital signal processor and dedicated hardware to achieve increased performance. In addition, the device includes a programmable video direct memory access (VDMA) controller to retrieve video data from memory in response to a command specifying a multidimensional block of video data.

Processing digital video data

The velocity of a wireless communications device () is estimated. In response to this estimate, a filter bandwidth, such as a pilot filter () bandwidth, is adjusted so that the introduction of noise and distortion to a signal received by the device is mitigated. The filter bandwidth is adjusted by increasing it as the estimated velocity increases; and decreasing it as the estimated velocity decreases. Such adjustments may be accomplished through providing a number of predetermined bandwidths that each correspond to a particular velocity range, and setting the filter bandwidth to the predetermined bandwidth that corresponds to the estimated velocity.

Velocity responsive filtering for pilot signal reception

Techniques to acquire and track pilots in a CDMA system. In an aspect, frequency acquisition of a number of signal instances (i.e., multipaths) in a received signal may be achieved concurrently based on a frequency control loop (RAFC) maintained for each finger processor of a rake receiver. Upon successful acquisition, frequency tracking of acquired multipaths may be achieved based on a combination of a frequency control loop (VAFC) maintained for an oscillator used for downconverting the received signal and the RAFCs for the finger processors. In a tracking mode, the VAFC tracks the average frequency of the acquired multipaths by adjusting the frequency of the oscillator. The RAFC of each finger processor tracks the residual frequency error (e.g., due to Doppler frequency shift) of the individual acquired multipath by adjusting the frequency of a complex sinusoidal signal used in a rotator within the finger processor.

Method and apparatus for acquiring and tracking pilots in a CDMA communication system

Growing community of inventors

San Diego, CA, United States of America

Gilbert Christopher Sih