International Business Machines Corporation

Cadence Design Systems, Inc.

Gilbert C Vandling

Howard Thomas Olnowich

Peter Michael Kogge

Joseph Michael Swenton

Thomas Norman Barker

Sameer Chakravarthy Chillarige

Anil Malik

Sharjinder Singh

In order to detect and locate defects, or faults, in a plurality of chips or other circuits sharing a common design, said chips are each tested for incorrect outputs, or failures, in response to inputs. The incorrect outputs are then collectively diagnosed in a single simulation by simulating a series of suspected fault candidates on a simulated chip of the chip design, and afterward comparing the incorrect outputs generated by each fault candidate to the incorrect outputs of the individual chips, to determine if a fault candidate generates all failures for a chip and no others. The test inputs and expected outputs may be predetermined through Automatic Test Pattern Generation. The fault candidates may be determined by use of a backtrace process such as back cone tracing. The failures may be recorded in association with a measure point, the input pattern that resulted in the failure, and the failure value.

Method and system of collective failure diagnosis for multiple electronic circuits

Disclosed are novel methods and apparatus for transforming sequential logic designs into equivalent combinational logic. In an embodiment of the present invention, a design method for transforming sequential logic designs into equivalent combinational logic is disclosed. The design method includes: simulating each stage of a clocking sequence to produce simulation values; saving the simulation values; and performing a plurality of backward logic traces based on the saved simulation values to provide an equivalent combinational logic representation of a sequential logic design.

Methods and apparatus for transforming sequential logic designs into equivalent combinational logic

A high priority path is added to the normal low priority path through a multi-stage switching network. The high priority path is established at the quickest possible speed because the high priority command is stored at the switch stage involved and made on a priority basis as soon as an output port becomes available. In addition, a positive feedback is given to the node establishing the connection immediately upon the making of the connection so that it may proceed at the earliest possible moment. The high priority path is capable of processing multiple high priority pending requests, and resolving the high priority contention using a snapshot register which implements a rotating priority such that no one requesting device can ever be locked out or experience data starvation. A dual priority switching apparatus with input port connections to output port connections uses as asynchronous means to resolve contention under low priority and the absence of blockage conditions, and switches automatically to a priority driven synchronous means of resolving contention. The protocol requires several parallel data lines plus four control lines so that the switching apparatus can be used for networks having a plurality of nodes, each node having a plurality of input and output ports, with a multiplexer control circuit for each output port for connecting any of I inputs to any of Z outputs, where I and Z can assume any unique value greater or equal to two. The switch has a single physical network path element over which either a low priority or high priority path can be established.

Dual priority switching apparatus for simplex networks

A triple modular redundancy computing system including three asynchronously connected processing elements, each having its own memory, a plurality of arbiters cross connecting processor elements for enforcing synchronization for tasks and for voting arbitration on output and without voting for inputs.

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Endicott, NY, United States of America

Gilbert C Vandling