International Business Machines Corporation

Gilad Merran

Eyal Naor

Erez Barak

Yair Fried

Oz Dov Hershkovitz

Avraham Ayzenfeld

Yossi Shapira

Amir Turi

Yanai Danan

Amit Shay

Oren Ben Gigi

Omri Rafaeli

In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.

Processor dependency-aware instruction execution

Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.

Error checking of a multi-threaded computer processor design under test

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Petach Tikva, Israel

Gilad Merran