Qualcomm Incorporated

Gilad Meir Sthoeger

Alexander Khazin

Michael Zilbershtein

Ben Levin

Lior Amarilio

Eyal Skulsky

Haim Hagay Haller

Felix Kolmakov

Michael Zilberstein

Alexander Golubitski

A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.

System and method of sending data via additional secondary data lines on a bus

Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device. The delay circuit includes two shift register chains configured to receive an output enable in signal based on a slow clock. A first shift register chain is clocked by a positive edge of a fast clock, and provides a first strobe signal. A second shift register chain is clocked by a negative edge of the fast clock, and provides a second strobe signal. The logic uses the first and second strobe signals, and the output enable in signal, to provide a delayed output enable out signal. The delay circuit provides a highly accurate time delay for the output enable signal to reduce or avoid data hazards in an area and power efficient manner.

Delay circuits and related systems and methods

Systems and methods to detect errors and record actions on a bus are disclosed. In one embodiment, the bus is a serial low-power interchip media bus (SLIMbus) within a computing device. The SLIMbus is coupled to peripherals and a sniffer is positioned within the computing device and coupled to the SLIMbus. The sniffer mimics another SLIMbus peripheral. However, the sniffer uses a pair of multiplexers to know when to record data on the SLIMbus. The data, including the control header and payload of the data signal is captured and logged. The logged data is then exported to memory where it can be further processed so as to help debug communication on the SLIMbus.

Systems and methods for detecting errors and recording actions on a bus

Exemplary embodiments are directed to broadcasting data on a USB system. The system includes a USB host and multiple broadcast-capable USB devices. Each USB device includes at least a default control endpoint for receiving control information and an isochronous sink endpoint for receiving a broadcast stream. The USB host programs a shared device address to an address register of each USB device such that all broadcast-capable USB devices programmed to that shared device address will accept the broadcast stream. One of the USB devices at the shared device address is set as a primary broadcast slave that will respond to non-isochronous transfers to the shared device address. All other USB devices with the shared device address are set to secondary slaves that ignore non-isochronous transfers to the shared device address.

Growing community of inventors

Givat-Ada, Israel

Gilad Meir Sthoeger