Microsoft Technology Licensing, LLC

Gilad Kirshenboim

Douglas Christopher Burger

Ori Laslo

Ran Sahar

Yehonathan Refael Kalim

A memory system may monitor a bit error rate in data read from a memory in the memory system. The memory system may determine that the monitored bit error rate satisfies an acceptable memory error condition. The memory system may adjust operation of the memory system to decrease the power consumption of the memory system, wherein the adjusted operation results in a new bit error rate monitored from data read from the memory that satisfies the acceptable memory error condition.

Adjusting memory power consumption

Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) processing elements (PEs). Selective variation of the precision of an array of MAC PEs may reduce power consumption of a neural processor. Power may be conserved by dynamically controlling the precision of analog to digital (ADC) output bits for one or more MAC PEs. Dynamic control of ADC output bit precision may be based on precision information determined during training and/or post-training (e.g., quantization) of an artificial intelligence (AI) neural network (NN) model implemented by the neural processor. Precision information may include a range of dynamic precision for each of a plurality of nodes of a computation graph for the AI NN model.

Growing community of inventors

Petach Tiqva, Israel

Gilad Kirshenboim