Dsp Group Limited

Ceva D.s.p. Ltd.

Mplicity Ltd.

Corage Ltd.

Gil Vinitzky

Eran Dagan

A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.

Chip area optimization for multithreaded designs

A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a second memory index denoting memory positions in the second memory space, the logical position of the elements within the ordered elements indexed by an element index, the method including bit-reversing the element index of a selected element, locating the selected element as being in the first memory space where the MSB of the bit-reversed index equals 0 and the second memory space where the MSB of the bit-reversed index equals 1, and locating the position of the selected element within the MSB-located memory space at the memory index of the MSB-located memory space that corresponds to the non-MSB bits of the bit-reversed index.

Bit-reversed indexing in a modified harvard DSP architecture

A method for advancing pointers in a memory including a sequence of N data points of a stage M of a Fast Fourier Transform (FFT) whose first stage is stage 0, the N data points including N/2 a data points and N/2 B data points, the N data points are stored in the memory in 2 groupings of a data points, each of the groupings having 2 data points, and each of the groupings is followed by a grouping of 2 B data points, the method including the steps of a) setting a pointer index A equal to the binary value of the data point memory index corresponding to the first A data point in the memory, b) setting a pointer index B equal to the binary value of the data point memory index corresponding to the first B data point in the memory, c) setting a first binary bit mask value R equal to 2 &plus;1, d) setting a second binary bit mask value R equal to 2 , e) advancing the B pointer index to the data point memory index corresponding to the next B data point in the memory by e1) adding the A pointer index value to R , e2) ORing the results of step e1) with R , and e3) setting the B pointer index value equal to the results of step e2), and f) advancing the A pointer index to the data point memory index corresponding to the next A data point in the memory by f1) adding the A pointer index value to R , f2) ANDing the results of step f1) with the bit-inverted value of R , and f3) setting the A pointer index value equal to the results of step f2).

FFT pointer mechanism for FFT memory management

A digital signal processor (DSP) includes at least two multipliers, at least two three-input arithmetic logic units (ALU), at least two first-cycle registers, at least two second-cycle registers, and multiplexing apparatus. The digital signal processor is able to perform a Fast Fourier Transform (FFT) calculation in two consecutive processing cycles.

Two cycle FFT

A device for performing a search for the optimum code vector in a codebook having N code vectors indexed by i has a controller which considers each ith code vector, and a processor which determines in two clock cycles whether said ith code vector is the current optimal code vector.

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Azur, Israel

Gil Vinitzky