Azul Systems, Inc.

Nortel Networks Corporation

Gil Tene

Michael A Wolf

Cliff N Click, Jr

Jack H Choquette

Shyam Prasad Pillalamarri

Murali Sundaresan

Ivan Posva

Scott D Sellers

Sivakumar Annamalai

Daniel Dwight Grove

Philip Reames

Anirban Sengupta

Adrian E Sun

Tom Kraljevic

Kevin B Normoyle

Luca Andrea Castellano

Simon Bryden

Anthony L Alles

Bryan Gleeson

Reinaldo Penno Filho

David Kruckernyer

A first instance of a managed runtime environment is provided. An optimized version of a code unit and a corresponding set of one or more speculative assumptions are received at the first instance of the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, and wherein the optimized version of the code unit and the corresponding set of one or more speculative assumptions are generated by an entity that is different from the first instance of the managed runtime environment. The optimized version of the code unit is executed at the first instance of the managed runtime environment. Whether the set of one or more speculative assumptions hold true is monitored at the first instance of the managed runtime environment.

Code optimization for connected managed runtime environments

A method of providing by a code optimization service an optimized version of a code unit to a managed runtime environment is disclosed. Information related to one or more runtime conditions associated with the managed runtime environment that is executing in a different process than that of the code optimization service is obtained, wherein the one or more runtime conditions are subject to change during the execution of the code unit. The optimized version of the code unit and a corresponding set of one or more speculative assumptions are provided to the managed runtime environment, wherein the optimized version of the code unit produces the same logical results as the code unit unless at least one of the set of one or more speculative assumptions is not true, wherein the set of one or more speculative assumptions are based on the information related to the one or more runtime conditions.

Code optimization conversations for connected managed runtime environments

A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically, and wherein the plurality of instruction units includes one or more memory modification instructions; in response to executing an instruction to commit inserted into the plurality of instructions units, incrementally commit a portion of the one or more memory modification instructions that have been atomically executed so far; and subsequent to incrementally committing the portion of the memory modification instructions that have been atomically executed so far, continue atomic execution of the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.

Enhanced managed runtime environments that support deterministic record and replay

A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units is not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and establish an incidentally atomic sequence of instruction units based at least in part on detection of the atomicity terminating event, wherein the incidentally atomic sequence of instruction units correspond to a sequence of instruction units in the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.

Detecting and recording atomic execution

A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units in the thread are not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and commit at least some of the one or more memory modification instructions. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.

Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.

Accelerated class check

Indicating usage in a system includes implementing a performance counter associated with one or more hardware threads; counting events associated with the one or more hardware threads to determine an event count; deriving an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count; applying a corrective function to modify the initial measure of usage and determine a modified measure of usage, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and outputting an indication of a processor usage, the indication being based at least in part on the modified measure of usage.

CPU utilization metering on systems that include multiple hardware threads per core

Managing interrupts in a computing environment includes executing an instruction, deriving an interrupt mask value based at least in part on the instruction being executed, performing a masking operation involving the interrupt mask value and at least one pending interrupt to determine whether a pending interrupt is allowable, and in the event that the pending interrupt is allowable, performing the interrupt.

Instruction based interrupt masking for managing interrupts in a computer environment

Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.

Cooperative preemption

A multiple processor system is disclosed. The processor system includes a first cluster including a first plurality of processors is associated with a first cluster cache, a second cluster including a second plurality of processors associated with a second cluster cache, and a cluster communication network between the first cluster and the second cluster for sharing data between the first cluster and the second cluster. The first cluster includes a first unshared connection to the cluster communication network and the second cluster includes a second unshared connection to the cluster communication network.

Multiple cluster processor

Executing a set one or more instructions is disclosed. A set of one or more register states is saved in a software data structure. The set of instructions is speculatively executed. At least one store made to a memory location during the speculative execution is not committed until the speculative execution is successfully completed. If an abort indication is received, the state of one or more registers restored.

Growing community of inventors

Los Altos Hills, CA, United States of America

Gil Tene