Samsung Electronics Co., Ltd.

Gil-Su Kim

Sung-Min Seo

Je-Min Ryu

Jong-Min Oh

Ho-Young Song

Seong-Jin Jang

Kyo-Min Sohn

Yong-Ho Cho

Ki-hong Kim

Soo-Won Kim

Yun-Young Lee

Je-Min Yu

Kyu-Chang Kang

Woo-Jin Rim

Woo-Kwan Lee

A decoupling circuit and a semiconductor device including the same are provided. The decoupling circuit includes a first circuit including a first capacitor having a first end connected to a first terminal, a first switch device connected between a second end of the first capacitor and a second terminal, and a first control device configured to turn on/off the first switch device based on a voltage level of the a second end of the first capacitor, and a second circuit including a second capacitor having a first end connected to the first terminal, a second switch device connected between a second end of the second capacitor and the second terminal, and a second control device configured to turn on/off the second switch device based on a voltage level of the second end of the second capacitor and an output signal of the first control device.

Decoupling circuit and semiconductor device including the same

A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Fuse data reading circuit having multiple reading modes and related devices, systems and methods

Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Semiconductor memory device having OTP cell array

A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Repair circuit and fuse circuit

A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Memory device, method of operating the same, and electronic device having the memory device

In a data transmitter, a main line driver circuit transmits an input signal to a receiver via a channel. A pre-emphasis circuit emphasizes a voltage level of the transmitted input signal, and a pre-emphasis controller controls the pre-emphasis circuit. The pre-emphasis controller adjusts a pre-emphasis level of the pre-emphasis circuit to increase an amount of current supplied to the channel at a transition time of the input signal in accordance with the transition condition of the channel.

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Hwaseong-si, South Korea

Gil-Su Kim