Mellanox Technologies Tlv Ltd.

Mellanox Technologies, Ltd.

Marvell Israel (Misl) Ltd.

Marvellworld Trade Ltd.

Marvell Israel (m.l.s.l) Ltd.

Marvell Isreal (m.i.s.l.) Ltd.

Marvell Israel Ltd.

Gil Levy

Aviv Kfir

Nafea Bshara

Nafea Bishara

Liron Mula

Carmi Arad

Salvatore Pontarelli

Pedro Reviriego

Barak Gafni

Amir Roitshtein

Niv Aibester

Rami Zemach

Aron Wohlgemuth

Alex Shpiner

Evgeny Shumsky

Benny Koren

Shira Turgeman

Zachy Haramaty

George Elias

Matty Kadosh

Lior Valency

Amir Rosen

Aviran Kadosh

Daniel Marcovitch

Yuval Shpigelman

Yamin Friedman

Sagi Lahav

Adar Peery

Sharon Ulman

Arye Albahari

Lion Levi

Itamar Rabenstein

Shie Mannor

Jakob Carlström

Sagi Kuks

Uri Safrai

Kurt Thomas Boden

Ariel Szapiro

Nir Monovich

Galia Peleg

Amit Rahav

Fima Kravchik

Idan Burstein

Eitan Zahavi

David Ben-Eli

Danny Alexander

Dror Goldenberg

Avi Urman

Roni Bar Yanai

Shachar Raindel

Amit Wix

Dror Bromberg

Lavi Koch

Andrey Ger

Itay Peled

Aviad Levy

Ehud Sivan

Omer Shabtai

Ran Sandhaus

Yonatan Piasetzky

Jacob Ruthstein

Yaron Zimerman

Shy Zimmerman

Maty Golovaty

Ohad Zalcman

Linor Nehab

Oded Belfer

Efim Yehiel Kravchik

Binyamin Altalef

Dekel Guterman

Michael Taher

Elad Alon

Tom Remen

A network device, system-on-a-chip, and method of performing packet handling are described. A packet is received, and a lookup based on one or more packet header fields of the packet is performed using a lookup generator action handler. An artificial intelligence engine processes packet header data associated with the packet, and a smart indication is generated. A forwarding decision is made for the packet based on the lookup performed by the lookup generator action handler as well as based on the smart indication generated with the artificial intelligence engine.

Systems and methods of packet classification using artificial intelligence

In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to control the prefetcher engines according to configurations of the prefetcher engines selected by a machine learning agent in exploration phases and in exploitation phases during execution of the software application, and execute the machine learning agent to select from a pruned set of configurations to control the prefetcher engines in the exploration phases, perform measurements on the system during execution of the machine learning agent, and execute the machine learning agent to select from the configurations to maximize potential rewards from controlling the prefetcher engines in the exploitation phases based on the performed measurements.

Prefetcher engine configuration selection with multi-armed bandit

A network device includes a memory and a memory management circuit. The memory is to store a shared buffer. The memory management circuit is to estimate respective bandwidth measures for one or more queues used in processing packets in the network device, and to allocate and deallocate segments of the shared buffer to at least one of the queues based on the bandwidth measures.

Queue bandwidth estimation for management of shared buffers and allowing visibility of shared buffer status

In one embodiment, a system includes prefetcher engines to predict next memory access addresses of a memory from which to load data to a cache during execution of a software application, and load the data from the predicted next memory access addresses to the cache during execution of the software application, and a processor to assign cache replacement precedence values to cache lines based on the prefetcher engines that loaded the cache lines, and evict the cache lines from the cache based on the cache replacement precedence values of the cache lines.

Cache replacement system

In one embodiment, a system includes a processor to reduce a number of cache replacement precedence value policies available for selection by a machine learning agent, each cache replacement precedence value policy including an array of predefined cache replacement precedence values for corresponding different combinations of (a) prefetcher engines that loaded cache lines, and (b) event-types of events that have been performed on the cache lines, and a memory to store data used by the processor.

Reducing set of policies with two or more hyper-dimensions

A networking device and system are described, among other things. An illustrative system is disclosed to include a shared buffer and at least a flow controller. In some embodiments, the system and/or flow controller may be configured to measure a packet flow's bandwidth consumption of the shared buffer, assign a flow-type attribute to the packet flow based on the packet flow's bandwidth consumption of the shared buffer, select a shared buffer schema for the packet flow based on the flow-type attribute assigned to the packet flow, and apply the selected shared buffer schema to the packet flow. For example, the flow-type attribute assigned to the packet flow may comprise a mice flow state or an elephant flow state, and a reserve attribute may be assigned to the flow based on the packet flow being assigned the mice flow state or the elephant flow state.

Mice-elephant aware shared buffer schema

A network device includes multiple ports, a Shared Buffer (SB) and a SB controller. The ports to connect to a communication network. The SB to temporarily store packets received from the communication network via the ports, the packets belonging to multiple flows. The SB controller to allocate one or more flow-specific storage regions in the SB, a given flow-specific storage region being allocated to store the packets that (i) belong to respective one or more of the flows and (ii) are to be transmitted via a respective egress queue. In response to detecting that an occupancy level in the given flow-specific storage region exceeds a specified occupancy threshold, the SB controller to report the flows in the given flow-specific storage region as congested.

Flow-based congestion control

Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information. Related apparatus and methods are also provided.

Global policers

A network device includes one or more ports, and action-select circuitry. The ports are to exchange packets over a network. The action-select circuitry is to determine, for a given packet, a first search key based on a first header field of the given packet, and a second search key based on a second header field of the given packet, to compare the first search key to a first group of compare values, to output a multi-element vector responsively to a match between the first search key and a first compare value, to generate a composite search key by concatenating the second search key and the multi-element vector, to compare the composite search key to a second group of compare values, and, responsively to a match between the composite search key and a second compare value, to output an action indicator for applying to the given packet.

Efficient memory utilization for cartesian products of rules

In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the timer is activated responsively to a quantity of the multiple missing data packets.

Out-of-order packet processing

A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

Template-based packet parsing

A network device includes one or more ports, and action-select circuitry. The ports are to exchange packets over a network. The act-ion-select circuitry is to determine, for a given packet, a first search key based on a first header field of the given packet, and a second search key based on a second header field of the given packet, to compare the first search key to a first group of compare values, to output a multi-element vector responsively to a match between the first search key and a first compare value, to generate a composite search key by concatenating the second search key and the multi-element vector, to compare the composite search key to a second group of compare values, and, responsively to a match between the composite search key and a second compare value, to output an action indicator for applying to the given packet.

A classification apparatus includes a memory and a processor. The memory is configured to store rules corresponding to a corpus of rules in respective rule entries, each rule includes a respective set of unmasked bits having corresponding bit values, and at least some of the rules include masked bits. The rules in the corpus conform to respective Rule Patterns (RPs), each RP defining a respective sequence of masked and unmasked bits. The processor is configured to cluster the RPs, using a clustering criterion, into extended Rule Patterns (eRPs) associated with respective hash tables including buckets for storing rule entries. The clustering criterion aims to minimize an overall number of the eRPs while meeting a collision condition that depends on a specified maximal number of rule entries per bucket.

Rule compilation schemes for fast packet classification

A network element includes one or more ports and a packet processor. The one or more ports are to transmit and receive packets over a network. The packet processor is to apply a plurality of rules to the packets, each rule specifying (i) expected values for each header field of a group of header fields of the packets, including, for a given header field in the group, at least a set of multiple expected values, (ii) a group ID associated with the set, and (iii) an action to be applied to the packets whose header fields match the expected values.

Optimizing header-based action selection

In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the tinier is activated responsively to a quantity of the multiple missing data packets.

Growing community of inventors

Hod Hasharon, Israel

Gil Levy