Broadcom Corporation

Novelics, LLC

Phillips Connect Technologies LLC

Mentor Graphics Corporation

Applied Materials, Inc.

Connected Holdings, LLC

Novelies, LLC

Norvelics, LLC

Gil I Winograd

Esin Terzioglu

Morteza Cyrus Afghahi

Ali Anvar

Sami Issa

Cyrus Afghahi

Zeynep M Toros

Bibhudatta Sahoo

Jim Epler

Melinda L Miller

Andreas Gotterba

Ahmad O Siksek

Lee H Veneklasen

Adam B Bean

Vidhya Krishnamurthi

Thomas Peterson

Adam Bean

William Cheney

Zhimin Guo

Zevnep M Toros

An automated asset monitoring system is provided for a towable asset. The system includes a power supply voltage that may be converted to power a monitored circuit during an active mode of operation while the towable asset is not connected to a tractor. The system powers the monitored circuit during the active mode so that a message regarding an operating condition of the monitored circuit may be transmitted by a telematics transceiver to a remote user.

Towable asset with automated monitoring

A system and method is provided to lock or unlock a gladhand coupler on a towed asset to prevent connection of a tractor air line to the gladhand is provided. The system prevents the tractor from properly operating the towed asset brakes and therefore prevents the unauthorized movement of the towed asset. The system has a locking mechanism that blocks the surface on the gladhand used for coupling with another gladhand coupler.

System and method for securing an asset

A method is described for operating an asset tracking device, wherein the tracking device normally collects many location points at a high periodic rate and transmits the location points as a single compressed location history data block at a low periodic rate, which greatly reduces the amount of transmitted data required to send a detailed location history. When a user begins actively viewing the asset location in some application such as on a mobile device, a command is immediately sent from the tracking server back to the tracking device. This command causes the device to start transmitting location reports at a high periodic rate, thereby allowing the user to monitor the current location of the asset in real-time. Transmission at the high data rate required for real-time monitoring only occurs while the user is actively interacting with the application, which is usually a short period of time.

Real-time asset location tracking and monitoring at a low data rate

The presence of a powered CAN bus is a good indicator of whether an aftermarket telematics device powered by a vehicle OBD port should enter a low-power mode to prevent unwanted battery drain, as the vehicle will remove power from the CAN bus when it determines the vehicle is not in use. Circuitry in the telematics device monitors the voltage on the CAN bus wires of the OBD port to determine whether the CAN voltage is above or below some threshold, such as 1V. This enables the vehicle ON/OFF status to be determined reliably without any additional wiring in the vehicle. The circuitry may include a simple, inexpensive, and low-power integrated circuit comparator, an operational amplifier, or an ADC to determine whether the vehicle is ON or OFF based on the CAN voltage. A very simple embodiment uses a single MOSFET and resistor to detect the vehicle ON/OFF state.

Apparatus and method for monitoring vehicle ON/OFF state

A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier.

Memory architecture with local and global control circuitry

A decoder for decoding an address having a plurality of bits ranging from a first address bit ato a last address bit a, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to ato an nth switch corresponding to a, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

NOR-OR Decoder

A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global sense amplifier operable to receive a sensed data state from the local sense amplifier.

NOR-OR decoder

A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a read operation or a write operation. The system can also include a sense amplifier in communication with a bit line of the memory block, and the sense amplifier can automatically shut off after indicating a sensed data state for the bit line. The controller may be a global controller or a local controller.

Synchronous global controller for enhanced pipelining

The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse.

The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Block redundancy implementation in hierarchical rams

In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.

Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer

A non-volatile memory cell includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.

Single-poly non-volatile memory cell

In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator.

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Irvine, CA, United States of America

Gil I Winograd