Micron Technology Incorporated

Lodestar Licensing Group LLC

Sony Deutschland Gmbh

Adv Antest Corporation

Gil Golov

Kishore Kumar Muchherla

Jeffrey S McNeil, Jr

Giuseppina Puzzilli

Todd A Marquart

Akira Goda

Mark Alan Helm

Jeremy Binfet

Carmine Miccoli

Niccolo' Righetti

Niccolo′ Righetti

Vamsi Pavan Rayaprolu

Karl David Schuh

Jiangang Wu

Zoltan Szubbocsev

Ashutosh Malshe

Robert Richard Noel Bielby

Piergiorgio Sartor

Ronald D Larson

Altfried Dilly

Ulrich Knoch

Alexander Scholz

Jörg Tappermann

Thomas Henkel

Alfried Dilly

An integrated circuit (IC) memory device encapsulated within an IC package. The memory device includes first memory regions configured to store lists of operands; a second memory region configured to store a list of results generated from the lists of operands; and at least one third memory region. A communication interface of the memory device can receive requests from an external processing device; and an arithmetic compute element matrix can access memory regions of the memory device in parallel. When the arithmetic compute element matrix is processing the lists of operands in the first memory regions and generating the list of results in the second memory region, the external processing device can simultaneously access the third memory region through the communication interface to load data into the third memory region, or retrieve results that have been previously generated by the arithmetic compute element matrix.

Parallel memory access and computation in memory devices

A one-time programmable (OTP) memory is included in both a memory device and a processing device. The OTP memories store encryption keys and the encryption and decryption of messages between the two devices are used as a heartbeat to determine that the memory device has not been separated from the processing device and, in some instances, connected to a malicious processing device.

Memory device with cryptographic kill switch

A scanning window is used to scan an image frame of a sensor when doing object detection. In one approach, positions within the image frame are stored in memory. Each position corresponds to an object detection at that position for a prior frame of data. A first area of the image frame is determined based on the stored positions. When starting to analyze a new frame of data, the first area is scanned to detect at least one object. After scanning within the first area, at least one other area of the new image frame is scanned.

Adapted scanning window in image frame of sensor for object detection

A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory.

Memory mapping for hibernation

A system including sensors of an advanced driver assistance system and a data recorder. The data recorder has: a volatile memory; a non-volatile memory configured with a file system region and a buffer region; and a processor configured to implement a file system mounted in the file system region. The data recorder records outputs from the sensors via the volatile memory into the buffer region in a cyclic way and, in response to an event, retrieve sensor data from the buffer region and store the sensor data into files organized under the file system mounted in the file system region.

Reduction of write amplification in sensor data recorders

Disclosed are devices and methods for improving the pre-booting of electronic control unit devices in vehicles. In one embodiment, a method is disclosed comprising detecting a triggering of a pre-booting condition based on one or more interactions with a vehicle; transmitting a power-on signal to at least one electronic control unit (ECU) in the vehicle, the at least one ECU operating in a low-power state; and fully booting the at least one ECU upon determining that the vehicle has been started.

Automotive electronic control unit pre-booting for improved man machine interface performance

A vehicle having a control element for the speed, acceleration or direction of the vehicle, two identical or redundant computing devices (e.g., each implemented as a system on chip (SoC)) to separately generate driving commands in parallel during autonomous driving of the vehicle, and a command controller coupled between the control element and the computing devices. In response to the commands from the identical or redundant computing devices, the command controller determines whether the commands are identical (or agree with each other); and if so, the command controller forwards one of the commands to the control element for execution. When there is a mismatch in the commands from the computing devices, the command controller tests the memories of the computing devices to identify a faulty one of the computing devices.

Determination of reliability of vehicle control commands via redundancy

An improved black box data recorder for use with autonomous driving vehicles (AVD). In one embodiment, two cyclic buffers are provided to record vehicle sensors data. A first cyclic buffer records raw vehicle sensor data on a volatile memory, while a second cyclic buffer records the same vehicle sensor data, as compressed data, on a non-volatile memory. In a case of a collision or near collision, in one embodiment the buffers are flushed into a non-volatile (NV) storage for retrieval. As long as there is no power interruption, the raw vehicle sensor data will be accessible from the NV storage. If a power interruption occurs, the raw vehicle sensor data held in the volatile memory of the first cyclic buffer will be lost and only the compressed form of the vehicle sensor data from the second cyclic buffer will survive and be accessible.

Black box data recorder for autonomous driving vehicle

A memory system having a processing device (e.g., CPU) and memory regions (e.g., in a DRAM device) on the same chip or die. The memory regions store data used by the processing device during machine learning processing (e.g., using a neural network). One or more controllers are coupled to the memory regions and configured to: read data from a first memory region (e.g., a first bank), including reading first data from the first memory region, where the first data is for use by the processing device in processing associated with machine learning; and write data to a second memory region (e.g., a second bank), including writing second data to the second memory region. The reading of the first data and writing of the second data are performed in parallel.

Parallel access to volatile memory by a processing device for machine learning

Systems, methods, and apparatus related to validating data stored in a memory system. In one approach, a DRAM stores data for a host device. A controller that manages the DRAM receives a command from the host device to generate a signature. The controller also receives data from the host device that indicates a region of the DRAM. In response to receiving the command, the controller reads data from the indicated region. A signature is generated by the controller based on the data read from the indicated region. The generated signature is sent to the host device in response to the command.

Validation of DRAM content using internal data signature

Methods, systems, and apparatuses related to reducing network congestion by analyzing data using a lightweight artificial intelligence (AI) layer prior to transmission are described. An AI model may predictively select data that need not be transmitted and, in some embodiments, further process data to be transmitted. As a result, the total size and amount of data transmitted over the network can be reduced, while the data needs of the receiving device can still be met. For example, data generated by a source application may be received and input into a predictive model, which may generate a prediction output for the data. The data may be pre-processed using a strategy selected based on the prediction output, and the pre-processed data may be transmitted over a network to a server.

Lightweight artificial intelligence layer to control the transfer of big data

A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Partitioned memory having error detection capability

A map in a cloud service stores physical objects previously detected by other vehicles that have previously traveled over the same road that a current vehicle is presently traveling on. New data received by the cloud service from the current vehicle regarding new objects that are being encountered by the current vehicle can be compared to the previous object data stored in the map. Based on this comparison, an operating status of the current vehicle is determined. In response to determining the status, an action such as terminating an autonomous navigation mode of the current vehicle is performed.

Determining autonomous vehicle status based on mapping of crowdsourced object data

A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

Growing community of inventors

Backnang, Germany

Gil Golov