Nxp B.v.

Nexperia B.v.

Gijs Jan De Raad

Da-Wei Lai

Guido Wouter Willem Quax

Denizhan Karaca

Madan Mohan Reddy Vemula

Paul Hendrik Cappon

Albert Jan Huitsing

Harrie Martinus Maria Horstink

Eric Thomas

Junfei Yu

Rongrong Tang

Haojing Wu

Yury Vladimirovich Alymov

Elena Valentinovna Somova

Mikhail Yurievich Semenov

Suzana Domingues

Marcus Van Der Vossen

An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.

Integrated circuit

Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current ('ESD current') and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

Cross-domain electrostatic discharge protection

Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

Transistor switches with electrostatic discharge protection

Embodiments of an ESD protection device are described. In an embodiment, an ESD protection device includes a first voltage rail electrically connected to a first node, a second voltage rail electrically connected to a second node, and ESD cells connected between the first and second voltage rails and configured to shunt current in response to an ESD pulse received between the first and second nodes. Each of the ESD cells includes clamp circuits electrically connected to the second voltage rail, ballast resistors connected between the first voltage rail and the clamp circuits, where at least some of the ballast resistors are electrically connected to a third voltage rail, a driver circuit connected between the second and third voltage rails and configured to generate a driver signal, and an output stage configured to generate an output signal in response to the driver signal.

Electrostatic discharge (ESD) protection device

An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.

Apparatus for suppressing parasitic leakage from I/O-pins to substrate in floating-rail ESD protection networks

A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event.

RC-triggered bracing circuit

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, the ESD protection circuit is connected between a Vrail and a Vrail and includes an internal floating ESD rail located between the Vrail and the Vrail, I/O pins connected between the internal floating ESD rail and the Vrail, ESD diodes corresponding to at least one I/O pin, an internal bias cell corresponding to an I/O pin and configured to short the corresponding I/O pin to the internal floating ESD rail when the I/O pin is pulled high, and an internal bias cell corresponding to a Vpin of the Vrail and configured to short the Vrail to the internal floating ESD rail when the Vpin is pulled high.

Electrostatic discharge (ESD) protection for use with an internal floating ESD rail

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.

Electrostatic discharge (ESD) protection device and method for operating an ESD protection device

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes an NMOS transistor configured to shunt current in response to an ESD pulse and a bigFET connected in parallel with the NMOS transistor. The NMOS transistor includes a source terminal, a gate terminal, and a body. The gate terminal and the body of the NMOS transistor are connected to the source terminal via a resistor. Other embodiments are also described.

An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area.

Electrostatic discharge protection device

An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

Electrostatic discharge power rail clamp circuit

A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.

Silicon controlled rectifier

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bigFET configured to conduct an ESD pulse during an ESD event. The bigFET includes a backgate terminal, a source terminal, and a current distributor connected to the backgate terminal and the source terminal and configured to homogeneously activate a parasitic bipolar junction transistor of the bigFET in response to a current that is generated in the bigFET during the ESD pulse. Other embodiments are also described.

BigFET ESD protection that is robust against the first peak of a system-level pulse

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

Growing community of inventors

Bemmel, Netherlands

Gijs Jan De Raad