National Semiconductor Corporation

Gideon Intrater

Oved Oz

Yachin Afek

Ohad Falik

Lev Epstein

Moshe Doron

Israel Greiss

Amos Intrater

Alberto Sandbank

Meir Tsadik

Omri Viner

Yehezkel Tzadik

Raya Levitan

Lior Katzri

Iddo Carmon

Ronny Cohen

Ilan Shimony

Gadi Erlich

Maurice Valentaten

Itael Fraenkel

Zvi Greenfeld

Yair Baydatch

Aharon Ostrer

Sidi Yomtov

Andy Birenbaum

Donald B Alpert

Chaim Bendelac

Zeev Collin

Alon Shacham

Jonathan Levy

Dan Biran

An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

Integrated digital signal processor/general purpose CPU with shared internal memory

A processor core for providing a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of a data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

Processor core which provides a linear extension of an addressable

An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

Integrated circuit having CPU core operable for switching between two

A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ('BIU') which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.

Microprocessor-based data processing apparatus that commences a next

The central processing unit of an integrated circuit data processing system includes both means for processing a first non-maskable interrupt (NMI) request received by the data processing system on a first NMI request line and means for processing a second NMI request received by the data processing system on a second NMI request line different from the first NMI request line and within a predefined time period after receipt of the first NMI request. Both. NMI requests are serviced by the data processing system even if the second NMI request is received prior to completion of processing of the first request.

Mechanism for handling non-maskable interrupt requests received from

The present invention is directed to various features of an integrated data processing system that includes a general purpose (GP) CPU core for processing data in accordance with a GP instruction set and a digital signal processor (DSP) module for processing data in accordance with command-list code. The DSP module is operable to execute the command-list code independent of and in parallel with execution of the GP instruction set by the CPU core. The system also includes test hook functions for facilitating production testing of the system.

Testing hooks for testing an integrated data processing system

Integrated digital signal processor/general purpose CPU with shared

An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal. The input port is connected to provide the output of the comparator as the input data signal to the central processing unit.

Integrated data processing system utilizing successive approximation

An integrated circuit structure, having a central processing unit (CPU) formed as a part thereof, for configuring the CPU for operating in an operating mode selected from a plurality of possible operating modes. The possible operating modes include a first possible operating mode that operates exclusively on internal memory storage elements, a second possible operating mode that operates exclusively on external memory storage elements via an external bus connected to a first portion of a plurality of general purpose I/O pins, and a third possible operating mode that operates on external memory storage elements via an external bus connected to a second portion of the general purpose I/O pins such that additional external I/O circuitry is necessary to handle I/O transfers.

Integrated data processing system including CPU core and parallel,

Parallel integrated circuit having DSP module and CPU core operable for

A directory for a plurality of information items stored in an electronic memory device is not retained in a continuous error-free portion of memory. Instead the memory area of the device is divided into blocks, with each block being assigned to no more than one information item. Each block is required to have a 'recoverable' portion of memory that need not be error-free but from which original data can be accurately read, with the assistance of an error correction algorithm, despite the presence of certain error(s). Directory data for a block are stored in such block, thereby markedly reducing the length of a continuous portion of memory needed to store the directory data.

Distributed directory for information stored on audio quality memory

Debug mechanism for parallel-operating DSP module and CPU core

An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

Integrated CPU core and parallel, independently operating DSP module and

A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

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Tel Aviv, Israel

Gideon Intrater