Samsung Display Co., Ltd.

Konkuk University Industrial Cooperation Corp

Gichang Lee

Kyungho Kim

Cholho Kim

Gunwoo Yang

Sangyong No

Sang Yong No

Wonjun Lee

Insoo Wang

Seungmin Lee

Jeongho Lee

Yongsoo Lee

Ju-Won Yoon

Dohyun Kwon

Choongyoul Im

Iljeong Lee

Sunkwun Son

Donghee Shin

Su-Yeon Sim

Jihoon Yang

Yongwoo Lee

Keechan Park

Yongjo Kim

Yikyoung You

Nokyung Park

A gate driver includes a first transistor including a control electrode, a first electrode receiving a previous signal and a second electrode electrically connected to a Q node, a second transistor including a control electrode electrically connected to the Q node, a first electrode receiving a first voltage and a second electrode electrically connected to a QB node, a third transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the QB node and a second electrode receiving a second voltage, a fourth transistor including a control electrode electrically connected to the QB node, a first electrode receiving the first voltage and a second electrode electrically connected to a GO node and a fifth transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the GO node and a second electrode receiving the second voltage.

Gate driver and display apparatus including the same

A gate driver includes a plurality of stages, each including: a first transistor including a first electrode, and a second electrode connected to a first control node; a third transistor including a first electrode connected to the first control node; and a second electrode connected to a second control node; a fifth transistor including a gate electrode connected to an inverting control node, and a second electrode connected to a gate output node; a sixth transistor including a gate electrode connected to the second control node, and a second electrode connected to the gate output node; a seventh transistor including a first electrode, and a second electrode connected to the first control node; and an eighth transistor including a gate electrode to receive an aging signal, a first electrode to receive an aging voltage, and a second electrode connected to the first electrode of the first transistor.

Gate driver and display device including the same

A pixel includes a first transistor coupled to a first node, a second transistor receiving a writing signal, a third transistor receiving a compensation signal, a first terminal coupled to the third node, and a second terminal coupled to a fourth node, a fourth transistor receiving an initialization signal, a first terminal coupled to the fourth node, and a second terminal coupled to an initialization voltage line, a fifth transistor receiving a first emission signal, a first terminal coupled to the first power supply voltage line, and a second terminal coupled to the second node, a light emitting element coupled to the third node and a second power supply voltage line, and an eighth transistor receiving a second emission signal, a first terminal coupled to the first node, and a second terminal coupled to the fourth node.

Pixel of a display device and display device

A stage of a gate driving circuit includes a first control circuit connected to a first voltage input terminal receiving a first voltage and a second voltage input terminal receiving a second voltage lower than the first voltage, the first control circuit being configured to control voltage levels of a first control node and a second control node; a first output circuit connected to a first clock terminal and a third voltage input terminal receiving a third voltage, the first output circuit being configured to output a gate signal according to the voltage levels of the first control node and the second control node; and a second output circuit connected to a second clock terminal and the second voltage input terminal, the second output circuit being configured to output a carry signal according to the voltage levels of the first control node and the second control node.

Gate driving circuit

A gate driving circuit includes: a first pull up control circuit for controlling a voltage of a pull up control node in response to a previous carry signal; a pull down control circuit for controlling a voltage of a pull down control node in response to the voltage of the pull up control node; a boosting circuit including a boosting capacitor and for boosting the voltage of the pull up control node; a gate output circuit for outputting a plurality of gate signals having different timings in response to the voltage of the pull up control node and the voltage of the pull down control node; and a stabilizing circuit including a control electrode connected to an end of the boosting capacitor, a first electrode for receiving a first high power voltage and a second electrode connected to the first pull up control circuit.

Gate driving circuit and display apparatus including the same

A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode receiving a carry signal, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first enable signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second enable signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode receiving the carry signal, a first electrode connected to the fifth node and a second electrode.

Gate signal masking circuit, gate driver including the same and display apparatus including the same

A display panel includes a first display region to an N-th display region disposed in a row direction. A P-th display region includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal, and a P-th region control circuit including a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, where the first control transistor and the second control transistor are controlled based on a P-th region control signal.

Display panel and display device including the same

A pixel may include a light emitting element; a first transistor electrically connected between a first node and a second node, the first transistor controlling a driving current provided to the light emitting element based on a voltage of a third node; a second transistor electrically connected between a data line providing a data signal and the first node, the second transistor being turned-on in response to a write gate signal; a third transistor electrically connected between the second node and the third node, the third transistor being turned-on in response to a compensation gate signal; and a bias transistor electrically connected between an emission control line providing an emission control signal and the first node, the bias transistor including a gate electrode electrically connected to the first node.

Pixel and display device including the same

A scan driver includes: stages. Each stage includes: a first node control circuit for controlling a voltage of a first node; an inverted carry node control circuit for controlling a voltage of an inverted carry node; a carry output circuit for outputting a carry signal; a fourth node control circuit for controlling a voltage of a fourth node in response to the carry signal; a second node control circuit for controlling a voltage of a second node in response to the carry signal, an enable signal, and the voltage of the inverted carry node; a third node control circuit for controlling a voltage of a third node in response to the voltage of the second node and the voltage of the fourth node; and a scan output circuit for outputting a scan signal in response to the voltage of the third node and the voltage of the fourth node.

Scan driver having a node control circuit in response to carry signal, enable signal, and voltage of inverted carry node and display device including the same

A gate driver including a plurality of stages. Each of the plurality of stages includes a first masking controlling circuit including a control circuit, a carry output circuit, a first enable node controlling circuit, a first masking circuit, a first gate output circuit, and a second masking controlling circuit including a second enable node controlling circuit, a second masking circuit and a second gate output circuit. The first masking controlling circuit and the second masking controlling circuit shares the control circuit and the carry output circuit.

A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal.

Transmission gate circuit, inverter circuit and gate driving circuit including the same

A pixel including a control transistor electrically connected between a gate of a switching transistor or another switching transistor and a node, and that controls a bias state of a driving transistor according to a voltage of a first gate signal for controlling turn-on of the switching transistor and a voltage of a second gate signal for controlling turn-on of the other switching transistor.

Pixel and display apparatus including the same

A scan driver includes a plurality of stages. Each of the plurality of stages includes a control circuit which controls a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal and a second clock signal, a carry output circuit which outputs a carry signal in response to the voltage of the first node and the voltage of the second node, an enable node controlling circuit which controls a voltage of an enable node in response to the carry signal, an enable signal and an inverted enable signal, a masking circuit which controls a voltage of a third node in response to the voltage of the second node and the voltage of the enable node, and a scan output circuit which outputs a scan signal in response to the voltage of the first node and the voltage of the third node.

Scan driver and display device

A light emitting display device includes: a first switch connected between a data line and a first node and including a gate connected to a first scan line; a second switch connected between a first driving power line and a second node and including a gate electrode connected to the first node; a first capacitor connected between the first node and the second node; a light emitting element connected between the second node and a second driving power line; a scan driver applying a first A-scan signal and a first B-scan signal during different times to the first scan line; a data driver applying a first initialization signal and a data signal to the data line at different times; and a power supply portion applying a first driving voltage, a second driving voltage, and a third driving voltage to the first driving power line at different times.

Light emitting display device

A display apparatus includes a gate line, a data line, and a pixel. The pixel includes first and second pixels displaying grayscales different from each other in response to a data voltage provided through the data line. The first pixel includes a first transistor including a gate electrode connected to the gate line and a first terminal connected to the data line and a first liquid crystal capacitor connected to a second terminal of the first transistor. The second pixel includes a second transistor including a gate electrode connected to the gate line and a first terminal connected to the second terminal of the first transistor and a second liquid crystal capacitor connected to a second terminal of the second transistor.

Growing community of inventors

Asan-si, South Korea

Gichang Lee