Microchip Technology Inc.

Zilog, Inc.

Gianpaolo Spadini

Randy L Yach

Kent D Hewitt

Donald S Gerber

Salvatore Spinella

Mihai C Manolescu

An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor

A method and circuits, in a non-volatile memory system such as EPROM, for limiting bit line current during programming that includes biasing a driving transistor to mirror a maximum desired current into the driving transistor from a mirroring transistor connected to a controlled current source. This technique is useful, for example, during hot electron programming of a floating gate memory cell to limit bit line current caused by snap back of the cell through which a relatively high current is passed. In a preferred embodiment, the state of a cell is monitored while being programmed by comparing the voltage of the bit line with a reference voltage that is developed in a circuit containing a replica of the driving transistor. Since characteristics of the driving and reference transistors are the same from wafer to wafer, or batch to batch, the reference voltage varies to compensate for variations in characteristics of the driving transistor among integrated circuit chips from different wafers and manufacturing batches.

Non-volatile memory program driver and read reference circuits

A method is described for a read-only MOS semiconductor memory. An addressable array of a multiplicity of cells each comprising a single MOS transistor is coded for preselected cells by providing them with source/drain regions which are spaced apart from edges of their respective overlying gate electrode regions. This is accomplished by a masking step late in the fabrication sequence. In this way, a dense MOS memory having rapid manufacturing turn-around is provided.

Method of fabricating a MOS read-only semiconductor memory array

Method and structure is disclosed for a read-only MOS semiconductor memory. An addressable array of a multiplicity of cells each comprising a single MOS transistor is coded for preselected cells by providing them with source/drain regions which are spaced apart from edges of their respective overlying gate electrode regions. This is accomplished by a masking step late in the fabrication sequence. In this way, a dense MOS memory having rapid manufacturing turn-around is provided.

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Mesa, AZ, United States of America

Gianpaolo Spadini