Texas Instruments Corporation

Gianluca Boselli

Charvaka Duvvury

John Eric Kunz, Jr

Akram Ali Salman

Farzan Farbiz

Jonathan S Brodsky

Aravind Chennimalai Appaswamy

Vijay Kumar Reddy

Ann Margaret Concannon

Ekanayake Ajith Amerasekera

Craig Thomas Salling

Jeremy Charles Smith

Muhammad Yusuf Ali

Rajkumar Sankaralingam

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

Electrostatic discharge devices

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Electrostatic discharge device

ESD robust MOS device

An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.

Mutual ballasting multi-finger bidirectional ESD device

An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.

Packaged device for detecting factory ESD events

A method of designing a diode includes generating a layout of the diode and calculating a calculated voltage overshoot based on the layout. The calculating includes calculating variables of: the length of an N region of the diode; current density during an ESD event; electron charge; hole mobility; electron mobility; doping concentration of the diode; and rise time of the ESD event.

Method for designing diodes

A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.

Twin-well lateral silicon controlled rectifier

Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

ESD protection validator, an ESD validation system and a method of validating ESD protection for an IC

An integrated circuit () formed at a semiconducting surface of a substrate including a common p-layer () includes functional circuitry () formed on the p-layer () including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (). At least one ESD protection cell (in more detail) is connected to at least one of the plurality of terminals of the functional circuitry (). The protection cell includes at least a first Nwell () formed in the p-layer (), a p-doped diffusion () within the first Nwell () to form at least one Nwell diode comprising an anode () and a cathode (). An NMOS transistoris formed in or on the p-layer () comprising a n+ source (), n+ drain () and a channel region comprising a p-region () between the source and drain, and a gate electrode () on a gate dielectric () on the channel region. The terminal of the functional circuit (, PAD) is coupled to the cathode () of the Nwell diode, and the anode () of the Nwell diode is connected in series with a path from the drain () to the source () of the NMOS transistor ().

MOS device with substrate potential elevation for ESD protection

A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

System, an apparatus and a method for performing chip-level electrostatic discharge simulations

An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.

Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system

An integrated circuit () formed at a semiconducting surface of a substrate including a common p-layer () includes functional circuitry () formed on the p-layer () including a plurality of terminals (IN, OUT, I/O) coupled to the functional circuitry (). At least one ESD protection cell (; in more detail) is connected to at least one of the plurality of terminals of the functional circuitry (). The protection cell includes at least a first Nwell () formed in the p-layer (), a p-doped diffusion () within the first Nwell () to form at least one Nwell diode comprising an anode () and a cathode (). An NMOS transistoris formed in or on the p-layer () comprising a n+ source (), n+drain () and a channel region comprising a p-region () between the source and drain, and a gate electrode () on a gate dielectric () on the channel region. The terminal of the functional circuit (, PAD) is coupled to the cathode () of the Nwell diode, and the anode () of the Nwell diode is connected in series with a path from the drain () to the source () of the NMOS transistor ().

MOS device with substrate potential elevation

A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element. In operation, the first terminal conducts current to the second terminal during a low impedance state in response to the altered trigger voltage being applied to the first terminal.

Low capacitance SCR with trigger element

A semiconductor device for locally protecting an integrated circuit input/output (I/O) pad () against ESD events, when the I/O pad is located between a power pad () and a ground potential pad (). A first diode () and a second diode () are connected in series, the anode () of the series connected to the I/O pad and the cathode () connected to the power pad. A third diode () has its anode () tied to the ground pad and its cathode () tied to the I/O pad. A string () of at least one diode has its anode () connected to the series between the first and second diode (node), isolated from the I/O pad, and its cathode () connected to the ground pad. The string () may comprise three or more diodes.

Growing community of inventors

Plano, TX, United States of America

Gianluca Boselli