Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Gianfranco Vai

Maurizio Zuffada

Giorgio Betti

Fabrizio Sacchi

David Macdara Moloney

Roberto Alini

Silvano Gornati

Rinaldo Castello

Valerio Pisati

Marco Gregori

Andrea Baschirotto

Melchiorre Bruccoleri

Marco Pio Demicheli

Salvatore Portaluri

Francesco Rezzi

Gaetano Cosentino

Loic Lietar

A BiCMOS transconductor differential stage for high frequency filters includes an input circuit portion having signal inputs and a pair of MOS transistors having their respective gate terminals corresponding to the signal inputs. The differential stage has an output circuit portion having signal outputs and a pair of bipolar transistors connected together with a common base inserted between the inputs and the outputs in a cascode configuration. The differential stage includes a switching device associated with at least one of the bipolar transistors to change the connections between parasitic capacitors present in the differential stage. The switching device also has at least one added bipolar transistor connected in a removable manner in parallel with the corresponding bipolar cascode transistor. In a variant differential stage, there are also provided respective added MOS transistors connected in parallel with the MOS transistors of the input circuit portion to change the ratio W:L of each of the MOS transistors.

BiCMOS transconductor stage for high-frequency filters

A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.

Fully integrable phase locked loop with low jitter

A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) connected between said output terminals (O1, O2) and the active load (4). Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

Transconductor stage with controlled gain

A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.

Apparatus for detecting undefined states of a finite state machine (FSM)

The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.

Circuit structure having distributed registers with self-timed reading

An integrated circuit transconductor stage which suppresses the dependence on temperature and production process variables of a differential transconductor stage. A negative feedback relation is used, where the output of the transconductor stage is connected to an additional current generator (which is referenced to a precision external resistor), to a capacitor, and also to the gate of a PMOS transistor which sources current to a polarization stage, which in turn sources current to the transconductor stage, or to multiple transconductor stages.

Differential transconductor with reduced temperature dependence

A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.

Circuit for neutralizing thermal drift in a transconductance stage

A circuit particularly useful in AGC systems, produces an output current which is proportional to the difference between a signal voltage and a reference voltage which is practically independent of temperature. By being a function of a ratio among actual values of integrated resistances and of a ratio among substantially temperature-stable voltages. The effects of temperature dependent value of integrated resistances and of temperature-dependent electrical characteristics of integrated semiconductor devices are compensated in order to produce the desired temperature-independent output current which may usefully be utilized for implementing an automatic gain control.

Apparatus and method for producing a temperature-independent current

A transconductor differential stage for high-frequency filters, which has a MOS differential input pair with common sources. The drain of each MOS input is connected to the emitter of an npn bipolar. These two matched bipolars have their gates connected together with the gate of a third bipolar, which is diode-connected. Two matched current sources feed the two bipolars, and a third current source feeds the third bipolar. A single controlled current sink is connected to the sources of both MOS input transistors, and also (through a resistor) to the third bipolar.

Transconductor stage for high frequency filters

In a dynamic automatic loop for control of the overall gain of an input circuit of a superheterodyne receiver, the response time of the HF-AGC circuit of the TUNER, in response to the action of the TUNER DELAY circuit activated by the IF-AGC in the case of autonomously uncontrollable abrupt increases in the level of the antenna signal from the same HF-AGC of the TUNER, is markedly reduced using an additional TUNER DELAY PLUS circuit able to absorb for a determined interval of time, a discharge current from the storage capacitor the control voltage of the HF-AGC in addition to the discharge current absorbed by the existing TUNER DELAY circuit. The relevant intensity of this additional discharge current and its duration are optimized by way of suitable circuital arrangements in the design of said TUNER DELAY PLUS circuit. The response time is reduced without modifying the time constant of the HF-AGC, which cannot be freely reduced because of inter- and cross-modulation problems.

Control loop for reducing the time of repsonse of a tuner-AGC of a

A circuit device for phasing an oscillator, which comprises a multivibrator having a transistor pair with the emitters coupled through a capacitor, comprises a normally open electronic switch controlled by a drive signal to close and inhibit the oscillator. This switch connects a voltage divider to the base of a transistor connected to one of the emitters to interrupt the loop positive feedback of the oscillator upon the voltage across the capacitor reaching a predetermined value.

Circuit device for phasing an oscillator

The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.

Tristate output gate structure particularly for CMOS integrated circuits

A control circuit for an oscillator comprising a multivibrator with transistors having their emitters connected in common and being supplied corresponding currents on respective legs, comprises a circuit structure adapted to produce on output terminals, on the one side, a current which is proportional to a reference current according to a predetermined parameter, and on the other side, a second current in turn correlated to the reference current as a function of said parameter, thereby to modify the oscillator duty cycle for a given operating frequency.

Control circuit for an oscillator

A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency. The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.

Method of automatically measuring the horizontal scan frequency of a

An electronic comparator device with hysteresis, being of a type which comprises a differential cell having a signal input, an output, and a threshold input, further comprises a second differential cell having one input connected to said output and the other input connected to a controlling circuit portion which has an output connected to the threshold input to reduce the threshold voltage value stepwise on the first change-over of the output of the comparator.

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Pavia, Italy

Gianfranco Vai