Motorola Corporation

International Business Machines Corporation

Intel Corporation

Gianfranco Gerosa

James Allan Kahle

Hector Adrian Sanchez

Aubrey Deene Ogden

Michael C Alexander

Jose M Alvarez

Arturo L Arizpe

Carl Lynn Shurboff

Bruce E Engles

Norman T Rollins

Mohammed Hasan Taufique

Harmander Singh

Rene M Delgado

Virgilio A Fernandez

Mohammad Mehedi Hasan

Horacio Mendez

Roger Countryman

Abhiman Pratap Kotwal

Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Voltage detector with high voltage protection

An electrostatic discharge (ESD) discharge circuit provides robust protection to an integrated circuit (13). In one embodiment, a resistive element (71) ensures that current shunting bipolar devices (60, 62, and 68) turn-on before devices within the integrated circuit are damaged by secondary breakdown. In another embodiment, a two terminal device (69) provides base current to a bipolar device (60) that shunts excess charge. This two terminal device enters gate aided junction breakdown as does an N-type MOSFET (72 and 74) but does not exhibit the same snap-back characteristics during ESD. Consequently, the two terminal device ensures that the ESD circuit tracks process modifications to the integrated circuit.

Electrostatic discharge (ESD) circuit

A method and circuitry are provided, in which a first operation is performed with first circuitry. A second operation is performed with second circuitry. A first signal is generated in response to the first operation. A second signal is generated in response to the second operation. Power consumption is adjusted within the second circuitry in response to the first and second signals.

Circuitry and method for reducing power consumption within an electronic

An electrostatic discharge protection device (12) may be fabricated below a wirebond pad (20) to reduce the area impact upon the circuit (10) which incorporates the device. The electrostatic discharge protection device has one or more diodes (13) formed below the wirebond pad. The connections to and from the diodes are by a one or more sets of strips (46). The silicon dioxide formed in the gaps between the strips transfers the downward force exerted during wirebonding to the substrate with causing interlayer delamination.

Electrostatic discharge protection device

A phase locked loop (10) has a first (24) and a second (28) feedback path by which a generated clock signal may be phase and frequency matched to an input reference clock signal. The two feedback paths are delay matched so either one may be used to maintain 'PLL lock.' However, the first path consumes significantly less power than the second path. Control circuitry (22) selects which path is fed back through a multiplexer (126) and disables the second path when the path is not needed.

Phase locked loop with low power feedback path and method of operation

A charge pump has a reference circuitry (18, 20, 22), a first parallel current path (16), at least one second parallel current path (16), a mirror circuit (46), a sourcing circuitry (60, 62) and a sinking circuitry (50, 54, 66, 68). The first and the at least one second parallel current path sink current from a first node responsive to a predetermined voltage generated by the reference circuitry. The at least one second current path also operates responsive to a control signal. The mirror circuit generates a second predetermined voltage responsive to the total current sunk from the first node. The sourcing circuitry and the sinking circuitry sourcing and sinking a current from the output node, respectively, responsive to the second predetermined voltage and to a control signal. The disclosed charge pump may be incorporated into a phase locked loop circuit where constant stability parameters are desired.

Charge pump with a programmable pump current and system

A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal. The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal. The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption. The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged.

High-speed low-power flip-flop

An output buffer integrated circuit, including an output signal, is provided having an improved Vdd and Vss noise characteristics. The output buffer comprise a plurality of pull-up stages and pull-down stages functioning as complementary pairs. The pull-up stage pulls the output signal to the Vdd potential, and the pull-down stages pulls the output to the Vss potential. Each stage provides a pulling signal to turn on a pulling transistor in response to the pulling signal of the previous stage. The first pulling stage provides the pulling signal in response to the input signal. Each stage sequentially pulls the output signal within a substantially constant time. The constant time delay within each stage is provided by sizing the width of the active elements on the integrated circuit. The pulling stages turn off the pulling transistors instantaneously in response to the invert of the input signal.

Output buffer having distributed stages to reduce switching noise

A CMOS differential amplifier or comparator circuit (100) is provided having minimized DC offset voltage. The circuit includes parallel coupled stages (110, 120, 130, 140, 150, 160) that are selectively controlled by an F.E.T. switch (182). The current through each stage is a function of its FET sizing. The current through the differential amplifier is adjusted by the selectively activated certain stages, which increase the current through differential amplifier (100), thereby adjusting the DC offset. The FETs in each stage are sized differently to allow flexibility in adjusting DC offset voltage.

Apparatus for adjusting DC offset voltage

An integrated circuit floating gate memory is formed using two layers of polysilicon. The first layer of polysilicon is patterned twice, once before the second polysilicon layer is deposited, and again as part of the etch of the second layer of polysilicon. Stringers of the second layer of polysilicon can form along the edge of the first etch of the first layer of polysilicon. The first etch of the first layer of polysilicon is patterned so that even if these stringers are subsequently formed, there is no harm.

Growing community of inventors

Austin, TX, United States of America

Gianfranco Gerosa