Stmicroelectronics S.r.l.

Consorzio Delta Ti Research

Sgsates Componenti Elettronici S.p.a.

Sgs-thomson Microelectronics S.r.l.

Sgs Microelettronica Spa

Istituto Guido Donegani S.p.a.

Erg S.p.a.

Gianfranco Cerofolini

Danilo Mascolo

Gianguido Rizzotto

Giuseppe Ferla

Dario Narducci

Giuseppe Paolo Crisenza

Giorgio De Santi

Giuseppe Queirolo

Giampiero Ottaviani

Laura Meda

A novel and effective structure of a stackable element (A, A) or more generally adapted to be associated modularly to other similar elements to form a septum of relatively large dimensions for a Seebeck/Peltier thermoelectric conversion device, may be fabricated with common planar processing techniques. The structure basically consists of a stack (A, A) of alternated layers of a first dielectric material (), adapted to be deposited in films of thickness lesser than or equal to about 50 nm, of low heat conductivity and which is etchable by a solution of a specific chemical compound, and of a second dielectric material () of low heat conductivity that is not etched by the solution. For the whole width, the stack is interrupted by parallel trenches (T, T, T) the width (w) of which may correspond to the minimum linewidth of definition allowed by the resolution of the lithographic process used for defining the parallel trenches, but which may eventually be limited by other parameters, in primis the height of the stack (h) to be subjected to the vertical etch to cut the stack in order to form the parallel trenches.

Seebeck/Peltier thermoelectric conversion element with parallel nanowires of conductor or semiconductor material organized in rows and columns through an insulating body and process

Significant phonon migration restraint is achieved within a relatively homogeneous polycrystalline doped semiconductor bulk by purposely creating in the crystal lattice of the semiconductor hydrocarbon bonds with the semiconductor, typically Si or Ge, constituting effective organic group substituents of semiconductor atoms in the crystalline domains. An important enhancement of the factor of merit Z of such a modified electrically conductive doped semiconductor is obtained without resorting to nanometric cross sectional dimensions in order to rely on surface scattering eventually enhanced by making the surface highly irregular and/or creating nanocavities within the bulk of the conductive material. A determinant scattering of phonons migrating under the influence and in the direction of a temperature gradient in the homogeneous semiconductor takes place at the organic groups substituents in the crystalline doped semiconductor bulk. Fabrication processes and Seebeck-Peltier energy conversion devices are exemplarily described.

Seebeck/peltier thermoelectric conversion device having phonon confinement layers of crystalline semiconductor containing angstrom-sized organic groups as semiconductor atoms substituents within the crystal lattice and fabrication process

The disclosure relates to Seebeck/Peltier effect thermoelectric conversion devices and in particular devices made of stack of dielectric layers alternated to treated semiconducting layers even of large size, not requiring lithographic patterning in a nano-micrometric scale.

Seebeck/peltier thermoelectric conversion device employing treated films of semiconducting material not requiring nanometric definition

A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Method for realizing a nanometric circuit architecture between standard electronic components and semiconductor device obtained with said method

A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.

Nanometric device with a hosting structure of nanometric elements

A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components. The method includes: providing a nanometric circuit architecture comprising a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above the succession, an insulating layer; opening, in the insulating layer, a window of nanometric width b extended along a direction inclined by an angle &#x3b1; with respect to the direction x to substantially cross the whole succession of nanowires, with exposure of a succession of exposed portions of the nanowires, one for each nanowire; realizing, above the insulating layer, a plurality of conductive dies extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies overlapping said window onto a respective exposed portion of a nanowire with obtainment of a plurality of contacts realizing said electric connections.

Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nanowire.

Electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

A method realizes a multispacer structure including an array of spacers having same height. The method includes realizing, on a substrate, a sacrificial layer of a first material; b) realizing, on the sacrificial layer, a sequence of mask spacers obtained by SPT, which are alternately obtained in at least two different materials; c) chemically etching one of the two different materials with selective removal of the mask spacers of this etched material and partial exposure of the sacrificial layer; d) chemically and/or anisotropically etching the first material with selective removal of the exposed portions of the sacrificial layer; e) chemically etching the other one of the two different materials with selective removal of the mask spacers of this etched material and obtainment of the multispacer structure.

Method for realizing a multispacer structure, use of said structure as a mold and circuital architectures obtained from said mold

A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n&#x2267;2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.

Nanometric structure and corresponding manufacturing method

A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.

Method and device for demultiplexing a crossbar non-volatile memory

A method realizes an electric connection between a nanometric circuit and standard electronic components. The method includes: providing, above a semiconductor substrate, a seed having a notched wall substantially perpendicular to the substrate, the wall having n recesses spaced apart from one another; and realizing n conductive nanowires alternated with insulating nanowires. Each realization of a conductive nanowire fills a corresponding recess by a respective elbow-like portion of the conductive nanowire, and partially fills the other recesses by respective notched profile portions, thereby forming the nanometric circuit. The method forms, above the nanometric circuit, an insulating layer; opens, in the insulating layer, n windows respectively corresponding with the recesses, thereby exposing the respective elbow-like portions; and realizes, above the insulating layer, n conductive dies addressed towards the standard electronic components and respectively overlapping the windows, thereby forming n contacts realizing the electric connection.

A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.

Hosting structure of nanometric elements and corresponding manufacturing method

Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n&#x2267;2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.

Method for realizing a hosting structure of nanometric elements

A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

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Milan, Italy

Gianfranco Cerofolini