Honeywell Information Systems Inc.

Honeywell Information Systems Italia

Giancarlo Tessera

Franco Ciacci

Vincenzo Pizzoferrato

Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectional gates directly connecting memory to the CPU or to the bus without interposition of registers, drivers, receivers, except said tridirectional gates, between the internal CPU channel and the memory channel. The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, absent such requests, the CPU may activate memory cycles in synchronism with its internal cycles without preamble diagloue and access waiting time. If I/OP memory access requests are pending, the control unit grants access to the I/OP on a priority basis, activates a memory cycle and monitors in time relation with the memory cycle if other I/OP memory access requests are pending, further granting memory access without delay at the end of the memory cycle. Absent further I/O memory access requests, the control unit resynchronizes its memory access request monitoring with the CPU internal cycles.

Data processing system architecture

A data processing system includes a control unit, working store and an operating section for performing operations upon information fetched from the working store. The operating section includes a plurality of independent, functionally different units. The control unit during the fetching and execution of program instructions enables a number of the units to perform different operations simultaneously upon the same information thereby increasing the overall speed of processing program instructions.

Electronic computer with independent functional networks for

An apparatus is disclosed for calling a microinstruction stored in main memory while another microinstruction from main memory is executing, thus permitting an overlap of the executing phase with the call phase of an instruction. A hardware sequencer examines predetermined characteristics of an executing microinstruction and takes appropriate action in response to such examination.

Growing community of inventors

Milan, Italy

Giancarlo Tessera