Sgs-Thomson Microelectronics S.r.l.

Giancarlo Ginami

Manlio Sergio Cereda

Claudio Brambilla

Andrea Ravaglia

Stefano Daffra

Enrico Laurin

Bruno Vajana

Silvia Lucherini

A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer ( ) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer ( ); c) forming over the whole integrated circuit a first layer of conductive material ( ); d) forming over the first layer of conductive material ( ) a layer of insulating material ( ); e) removing the layer of insulating material ( ) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material ( ) which in the memory cell array area is separated from the first layer of conductive material ( ) by the insulating material layer ( ), while outside the memory cell array area is directly superimposed over said first layer of conductive material ( ); g) inside the memory cell array area, defining first strips ( ) of the second layer of conductive material ( ) for forming rows ( ) of the memory cell array ( ), and outside the memory cell array area defining second strips ( ) of the second layer of conductive material ( ) for forming interconnection lines ( ) for electrically interconnecting the rows ( ) of the memory cell array with a circuitry ( RD), said defining the second strips ( ) providing for selectively etching the first and second layers of conductive material ( ) outside the memory cell array area by means of a first mask (MASK ), and said defining the first strips ( ) providing for selectively etching the second layer of conductive material ( ), the layer of insulating material ( ) and the first layer of conductive material ( ) inside the memory cell array area by means of a second mask (MASK ).

Process for manufacturing an integrated circuit comprising an array of memory cells

A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

Method for improving the intermediate dielectric profile, particularly

A process for manufacturing an integrated circuit comprising an array of memory cells, providing for: a) forming in a memory cell array area of a semiconductor layer (6) an active area for the memory cells; b) forming over said active area for the memory cells a gate oxide layer (8); c) forming over the whole integrated circuit a first layer of conductive material (9); d) forming over the first layer of conductive material (9) a layer of insulating material (10); e) removing the layer of insulating material (10) from outside the memory cell array area; f) forming over the whole integrated circuit a second layer of conductive material (11) which in the memory cell array area is separated from the first layer of conductive material (9) by the insulating material layer (10), while outside the memory cell array area is directly superimposed over said first layer of conductive material (9); g) inside the memory cell array area, defining first strips (22) of the second layer of conductive material (11) for forming rows (3) of the memory cell array (1), and outside the memory cell array area defining second strips (17) of the second layer of conductive material (11) for forming interconnection lines (100) for electrically interconnecting the rows (3) of the memory cell array with a circuitry (5,RD) said, first strips (22) and the second strips (17) of the second layer of conductive material (11) are automatically joined at respective ends thereof at said boundary region.

Process for manufacturing an integrated circuit comprising an array of

A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

Process for manufacturing MOS-type integrated circuits

A method of manufacture of a low-capacitance programmed cell structure for read-only memory circuits comprises a field-effect transistor having conventional source and drain regions separated by a channel region overlaid by the gate of the transistor. This ROM memory cell is programmed by a channel implant extending only from the source region for a selected distance into the channel region.

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Bergamo, Italy

Giancarlo Ginami